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51. 发明授权

US5885877A Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric 失效
标题翻译：复合栅电极，其与掺杂剂扩散阻滞层结合，邻近底层栅极电介质
公开(公告)号：US5885877A
公开(公告)日：1999-03-23
申请号：US837581
申请日：1997-04-21
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L29/49 , H01L21/336 , H01L21/3205
CPC分类号： H01L21/28035 , H01L29/4916
摘要： A composite gate electrode layer incorporates a diffusion-retarding barrier layer disposed at the bottom of the gate electrode layer to reduce the amount of dopant which diffuses into the gate dielectric layer from the gate electrode layer. A lower nitrogen-containing gate electrode layer provides a diffusion-retarding barrier layer against dopant diffusion into the gate dielectric layer disposed therebelow, and an upper gate electrode layer is formed upon the lower layer and is doped to form a highly conductive layer. Together the first and second gate electrode layers form a composite gate electrode layer which incorporates a diffusion-retarding barrier layer adjacent to the underlying gate dielectric layer. The barrier layer may be formed by annealing a first polysilicon layer in a nitrogen-containing ambient, such as N.sub.2, NO, N.sub.2 O, and NH.sub.3, by implanting a nitrogen-containing material, such as elemental or molecular nitrogen, into a first polysilicon layer, and by in-situ depositing a nitrogen-doped first polysilicon layer. Diffusion of dopants into the gate dielectric layer may be retarded, as most dopant atoms are prevented from diffusing from the composite gate electrode layer at all. In addition, the nitrogen concentration within the gate dielectric layer, particularly at or near the substrate interface, may be maintained at lower concentrations than otherwise necessary to prevent dopant diffusion into the underlying substrate. The present invention is particularly well suited to thin gate dielectrics, such as a those having a thickness less than approximately 60 .ANG. when using a p-type dopant, such as boron.
摘要翻译：复合栅极电极层包括设置在栅极电极层底部的扩散阻挡层，以减少从栅极电极层扩散到栅极电介质层中的掺杂剂的量。下部含氮栅电极层提供阻止扩散阻挡层，以阻止掺杂剂扩散到设置在其下方的栅介质层中，并且在下层上形成上栅极电极层，并且被掺杂以形成高导电层。第一和第二栅极电极层一起形成复合栅极电极层，该复合栅极电极层包含与下面的栅极电介质层相邻的扩散阻滞阻挡层。通过将含氮材料（例如元素或分子氮）注入到第一多晶硅层中，可以通过在氮气环境如N 2，NO，N 2 O和NH 3中退火第一多晶硅层来形成阻挡层，并通过原位沉积氮掺杂的第一多晶硅层。完全可以防止掺杂剂扩散到栅极电介质层中，因为大多数掺杂剂原子被阻止从复合栅极电极层扩散。此外，栅极电介质层内，特别是在衬底界面处或附近的氮浓度可以保持在比防止掺杂剂扩散到下面的衬底中所必需的更低的浓度。本发明特别适用于薄栅电介质，例如当使用诸如硼的p型掺杂剂时厚度小于约60的薄电介质。

52. 发明授权

US5882983A Trench isolation structure partially bound between a pair of low K dielectric structures 失效
标题翻译：沟槽隔离结构部分地结合在一对低K电介质结构之间
公开(公告)号：US5882983A
公开(公告)日：1999-03-16
申请号：US994143
申请日：1997-12-19
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21/762 , H01L21/326 , H01L21/76
CPC分类号： H01L21/76237
摘要： A process is provided for forming to dielectric structures having a relatively low dielectric constant arranged adjacent to the opposed lateral edges of a trench isolation structure. In an embodiment, an opening is etched vertically through a masking layer arranged upon a semiconductor substrate, thereby exposing the surface of the substrate. A patterned photoresist layer is formed upon the masking layer using optical lithography to define the region to be etched. Sidewall spacers made of a low K dielectric material are formed upon the opposed sidewall surfaces of the masking layer within the opening. The sidewall spacers are formed by CVD depositing a dielectric material within the opening and anisotropically etching the dielectric material until only a pre-defined thickness of the material remains upon the masking layer sidewall surfaces. Thereafter, a trench defined between the exposed lateral edges of the sidewall spacers is formed within the substrate. The sidewall spacers permit the lateral width of the spacers to be reduced below the minimum lateral dimension definable using lithography. A trench dielectric is formed within the trench such that the upper portion of the dielectric is bound by the sidewall spacers on opposite ends. The resulting trench isolation structure is less likely to experience current leakage when operating an ensuing integrated circuit which employs the isolation structure.
摘要翻译：提供了一种用于形成具有邻近沟槽隔离结构的相对侧边缘布置的相对低的介电常数的电介质结构的工艺。在一个实施例中，通过布置在半导体衬底上的掩模层垂直蚀刻开口，从而暴露衬底的表面。使用光刻法在掩模层上形成图案化的光致抗蚀剂层，以限定待蚀刻的区域。由低K电介质材料制成的侧壁隔离物形成在开口内的掩蔽层的相对的侧壁表面上。通过在开口内CVD沉积电介质材料并各向异性地蚀刻电介质材料形成侧壁间隔物，直到材料的预定厚度仅保留在掩模层侧壁表面上为止。此后，在衬底内形成限定在侧壁间隔物的暴露的横向边缘之间的沟槽。侧壁间隔件允许间隔物的横向宽度减小到使用光刻可定义的最小横向尺寸以下。在沟槽内形成沟槽电介质，使得电介质的上部由相对端上的侧壁间隔件结合。当使用隔离结构的随后集成电路进行操作时，所得到的沟槽隔离结构不太可能经历电流泄漏。

53. 发明授权

US5882974A High-performance PMOS transistor using a barrier implant in the source-side of the transistor channel 失效
标题翻译：在晶体管通道的源极侧使用栅极注入的高性能PMOS晶体管
公开(公告)号：US5882974A
公开(公告)日：1999-03-16
申请号：US57251
申请日：1998-04-08
申请人： Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21/265 , H01L21/266 , H01L21/336 , H01L29/78 , H01L21/425
CPC分类号： H01L29/66659 , H01L21/26506 , H01L29/7835 , H01L21/266
摘要： The present invention advantageously provides a method for forming a transistor having decreased source-side parasitic resistance and an improved shallow junction, thereby providing for enhanced transistor performance and improved resistance to short-channel effects. Barrier atoms are selectively implanted into the semiconductor substrate prior to formation of lightly doped drains and source/drain regions. Barrier atoms present in the channel region under the gate structure prevent migration of the lightly doped drain implant impurities into the channel region, thus reducing parasitic resistance. Barrier atoms implanted into the junction region prevent migration of source implant impurities more deeply into the junction region, thus preserving the shallow junction.
摘要翻译：本发明有利地提供了一种用于形成具有降低的源极侧寄生电阻和改善的浅结的晶体管的方法，从而提供增强的晶体管性能和改善的抗短路效应。在形成轻掺杂的漏极和源极/漏极区之前，将栅极原子选择性地注入到半导体衬底中。存在于栅极结构下方的沟道区域中的阻挡原子防止了轻掺杂的漏极注入杂质迁移到沟道区中，从而降低寄生电阻。注入接合区域的阻挡原子防止了源极注入杂质更深入到接合区域，从而保留了浅结。

54. 发明授权

US5872049A Nitrogenated gate structure for improved transistor performance and method for making same 失效
公开(公告)号：US5872049A
公开(公告)日：1999-02-16
申请号：US666017
申请日：1996-06-19
申请人： Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/51 , H01L21/3205 , H01L21/44
CPC分类号： H01L21/28202 , H01L21/28176 , H01L21/28211 , H01L21/823842 , H01L27/0928 , H01L29/518 , Y10S257/914
摘要： An integrated circuit fabrication method incorporating nitrogen into the polysilicon-dielectric interface in an MOS transistor. A semiconductor substrate having a P-well region and an N-well region is provided. Each well region includes channel regions and source/drain regions. A dielectric layer, preferably a thermal oxide, is formed on an upper surface of the semiconductor substrate. The thermal oxide can be grown in a nitrogen bearing ambient, an O.sub.2 ambient, or an H.sub.2 O ambient. Alternatively, the dielectric may be formed from a deposited oxide. Thereafter, a layer of polysilicon is formed on the dielectric layer and a plurality of "nitrogenated" polysilicon gates is formed on the dielectric layer over the channel regions. In a presently preferred embodiment, nitrogen species are introduced into the polysilicon gates with an ion implantation step. The nitrogen implantation step may alternatively be performed before or after the patterning of the polysilicon layer. If implantation occurs after patterning of the polysilicon layer, nitrogen will be introduced into the source/drain regions and effect an increase in drive current without a corresponding increase in leakage current. In a presently preferred embodiment, a dose of between 5.times.10.sup.13 cm.sup.-2 and 1.times.10.sup.16 cm.sup.-2 is used for implanting the nitrogen bearing species and the species is distributed within the plurality of polysilicon gates such that the concentration of the nitrogen is greatest at approximately a midpoint within said gates. The semiconductor substrate may be subsequently annealed in an ambient maintained between approximately 900.degree. to 1100.degree. C. preferably using a rapid thermal anneal apparatus.

55. 发明授权

US5854515A Integrated circuit having conductors of enhanced cross-sectional area 失效
公开(公告)号：US5854515A
公开(公告)日：1998-12-29
申请号：US685143
申请日：1996-07-23
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L23/522 , H01L23/528 , H01L23/52
CPC分类号： H01L23/5226 , H01L23/5283 , H01L2924/0002 , Y10S257/92 , Y10S257/923
摘要： A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.

56. 发明授权

US5854131A Integrated circuit having horizontally and vertically offset interconnect lines 失效
标题翻译：集成电路具有水平和垂直偏移的互连线
公开(公告)号：US5854131A
公开(公告)日：1998-12-29
申请号：US655245
申请日：1996-06-05
申请人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford Jr. , Fred N. Hause , William S. Brennan
发明人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/312 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/04 , H01L21/44
CPC分类号： H01L23/5222 , H01L23/5226 , H01L23/5283 , H01L2924/0002
摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. Accordingly, a space between conductors on one level is directly above or directly below a conductor within another level. The staggered interconnect lines are advantageously used in densely spaced regions to reduce the interlevel and intralevel capacitance. Furthermore, an interlevel and an intralevel dielectric structure includes optimally placed low K dielectrics which exist in critical spaced areas to minimize capacitive coupling and propagation delay problems. The low K dielectric, according to one embodiment, includes a capping dielectric which is used to prevent corrosion on adjacent metallic conductors, and serves as an etch stop when conductors are patterned. The capping dielectric further minimizes the overall intrinsic stress of the resulting intralevel and interlevel dielectric structure.
摘要翻译：提供了一种改进的多级互连结构。互连结构包括多个级别的导体，其中一个层上的导体相对于另一层上的导体交错。因此，在一个级别上的导体之间的空间位于另一层内的导体的正上方或正下方。交错的互连线有利地用于密集间隔的区域以减少层间和层间电容。此外，层间和层间电介质结构包括存在于临界间隔区域中的最佳放置的低K电介质，以最小化电容耦合和传播延迟问题。根据一个实施例的低K电介质包括封盖电介质，其用于防止相邻金属导体上的腐蚀，并且当导体被图案化时用作蚀刻停止层。封盖电介质进一步最小化所得到的层间和层间电介质结构的整体固有应力。

57. 发明授权

US5851893A Method of making transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection 失效
标题翻译：制造具有基本上耐漏极侧热载流子注入的栅极电介质的晶体管的方法
公开(公告)号：US5851893A
公开(公告)日：1998-12-22
申请号：US896680
申请日：1997-07-18
申请人： Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/28176 , H01L29/518 , H01L29/6659 , H01L29/7833 , H01L21/28194 , Y10S257/90 , Y10S438/91
摘要： A transistor fabrication process is provided which derives a benefit from having barrier atoms incorporated in a lateral area under a gate oxide of the transistor in close proximity to the drain. To form the transistor, a gate oxide layer is first grown across a silicon-based substrate. A polysilicon layer is then deposited across the gate oxide layer. Portions of the polysilicon layer and the oxide layer are removed to form a gate conductor and gate oxide, thereby exposing source-side and drain-side junctions within the substrate. An LDD implant is performed to lightly dope the source-side and drain-side junctions. An etch stop material may be formed upon opposed sidewall surfaces of the gate conductor, the upper surface of the gate conductor, and the source-side and drain-side junctions. Spacers may then be formed laterally adjacent the etch stop material located upon sidewall surfaces of the gate conductor. The unmasked portions of the source-side and drain-side junctions are heavily doped, resulting in source and drain regions that are aligned to the exposed lateral edges of the spacers. The drain-side spacer is removed and barrier atoms are forwarded through the exposed etch stop material and into a substrate/gate oxide interface region near the drain junction. The barrier atoms help reduce hot electron effects by blocking diffusion avenues of carriers (holes or electrons) from the drain-side junction into the gate oxide.
摘要翻译：提供了一种晶体管制造工艺，该方法得益于将栅极原子结合在晶体管的栅极氧化物附近在漏极附近的优点。为了形成晶体管，首先在硅基衬底上生长栅氧化层。然后在栅极氧化物层上沉积多晶硅层。去除多晶硅层和氧化物层的部分以形成栅极导体和栅极氧化物，从而暴露衬底内的源极侧和漏极侧结。进行LDD注入以轻轻地掺杂源极侧漏极和漏极侧结。蚀刻停止材料可以形成在栅极导体的相对的侧壁表面，栅极导体的上表面以及源极侧和漏极侧结。然后可以在位于栅极导体的侧壁表面上的蚀刻停止材料的横向邻近地形成间隔。源侧和漏极侧结的未屏蔽部分被重掺杂，导致源极和漏极区域与间隔物的暴露的侧向边缘对准。去除漏极侧隔离物，并且阻挡原子通过暴露的蚀刻停止材料并且进入到漏极结附近的衬底/栅极氧化物界面区域中。阻挡原子有助于通过阻止载流子（空穴或电子）从漏极侧结到扩散通道到栅极氧化物中来减少热电子效应。

58. 发明授权

US5847462A Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer 失效
标题翻译：集成电路具有具有蚀刻停止阻挡层的具有增强的横截面面积的导体
公开(公告)号：US5847462A
公开(公告)日：1998-12-08
申请号：US748812
申请日：1996-11-14
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan , Fred N. Hause , Robert Dawson , Mark W. Michael
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan , Fred N. Hause , Robert Dawson , Mark W. Michael
IPC分类号： H01L21/60 , H01L21/768 , H01L23/522 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L21/76816 , H01L21/76838 , H01L2924/0002
摘要： An interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.
摘要翻译：提供具有增强厚度的导体的互连结构。导体包括上部和下部，其中下部几何形状足以增加超过上部提供的载流能力。下部通过在上部电介质区域内填充沟槽而形成，并且通过从直接在下部的正上方的区域除去上电介质表面的导电材料形成上部。上部和下部由此形成增强横截面的导体，其可以通过修改通孔蚀刻掩模而不是必须重新配置和/或移动由金属掩模形成的互连特征而产生。

59. 发明授权

US5837572A CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein 失效
标题翻译： CMOS集成电路通过使用可移除间隔物在不对称PMOS结之间产生不对称的NMOS结形成，用于优化植入其中的掺杂剂的热扩散率
公开(公告)号：US5837572A
公开(公告)日：1998-11-17
申请号：US781461
申请日：1997-01-10
申请人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
IPC分类号： H01L21/8238 , H01L21/82
CPC分类号： H01L21/823814 , H01L29/66659 , H01L29/7835
摘要： An integrated circuit is provided having both NMOS transistors and PMOS transistors. The NMOS transistor junction regions are preferably formed before the PMOS transistor junction regions with pre-defined anneal temperatures applied after select implant steps. Both the NMOS and PMOS transistor junction are graded such that the drain areas include a relatively large LDD implant area and the source junctions do not. Whatever LDD area pre-existing in the source implanted with a higher concentration source/drain or MDD implant. The ensuing integrated circuit is therefore a CMOS circuit having asymmetrical transistor junctions and carefully controlled implant and anneal sequences. The asymmetrical junctions are retained, or at least optimized, by controlling the anneal temperatures such that diffusivity distances of n-type implants are relatively similar to p-type implants. Diffusivity is controlled by regulating the post-implant anneal temperatures of p-type implants lesser than previous n-type implants.
摘要翻译：提供具有NMOS晶体管和PMOS晶体管的集成电路。 NMOS晶体管结区优选地在具有预定义的退火温度的PMOS晶体管结区之后形成在选择的注入步骤之后。 NMOS和PMOS晶体管结都被分级，使得漏极区域包括相对较大的LDD注入区域，并且源极结不包括。无论在植入较高浓度源/漏或MDD植入物的源中预先存在LDD区域。因此，随后的集成电路是具有不对称晶体管结和仔细控制的注入和退火序列的CMOS电路。通过控制退火温度使得n型植入物的扩散距离相对于p型植入物保持或至少优化不对称结。通过调节比以前的n型植入物少的p型植入物的植入后退火温度来控制扩散性。

60. 发明授权

US5831306A Asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region 失效
标题翻译：具有轻掺杂漏极区域，重掺杂源极和漏极区域以及超重掺杂源极区域的非对称晶体管
公开(公告)号：US5831306A
公开(公告)日：1998-11-03
申请号：US823946
申请日：1997-03-25
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66659 , H01L29/7835
摘要： An asymmetrical IGFET including a lightly doped drain region, heavily doped source and drain regions, and an ultra-heavily doped source region is disclosed. Preferably, the lightly doped drain region and heavily doped source region provide channel junctions. A method of making the IGFET includes providing a semiconductor substrate, forming a gate with first and second opposing sidewalls over the substrate, applying a first ion implantation to implant lightly doped source and drain regions into the substrate, applying a second ion implantation to convert the lightly doped source region into a heavily doped source region without doping the lightly doped drain region, forming first and second spacers adjacent to the first and second sidewalls, respectively, and applying a third ion implantation to convert a portion of the heavily doped source region outside the first spacer into an ultra-heavily doped source region without doping a portion of the heavily doped source region beneath the first spacer, and to convert a portion of the lightly doped drain region outside the second spacer into a heavily doped drain region without doping a portion of the lightly doped drain region beneath the second spacer. Advantageously, the IGFET has low source-drain series resistance and reduces hot carrier effects.
摘要翻译：公开了一种包括轻掺杂漏极区域，重掺杂源极和漏极区域以及超重掺杂源极区域的非对称IGFET。优选地，轻掺杂漏极区域和重掺杂源极区域提供通道结。制造IGFET的方法包括提供半导体衬底，在衬底上形成具有第一和第二相对侧壁的栅极，施加第一离子注入以将轻掺杂的源极和漏极区域注入到衬底中，施加第二离子注入以将轻掺杂源区域分成重掺杂源区，而不掺杂轻掺杂漏极区，分别与第一和第二侧壁相邻形成第一和第二间隔，并施加第三离子注入以将重掺杂源区的一部分转换到外部所述第一间隔物进入超重掺杂源区，而不掺杂所述第一间隔物下方的重掺杂源区的一部分，以及将所述第二间隔区外部的所述轻掺杂漏极区的一部分转换为重掺杂漏极区，而不掺杂第二间隔物下方的轻掺杂漏极区的部分。有利地，IGFET具有低的源极 - 漏极串联电阻并且降低热载流子效应。

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