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51. 发明授权

US08375162B2 Method and apparatus for reducing write cycles in NAND-based flash memory devices 有权
标题翻译：用于减少基于NAND的闪存器件中的写周期的方法和装置
公开(公告)号：US08375162B2
公开(公告)日：2013-02-12
申请号：US12793023
申请日：2010-06-03
申请人： William J. Allen , Franz Michael Schuette
发明人： William J. Allen , Franz Michael Schuette
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： A NAND-based flash memory device and a method of its operation that extends the life of the device by reducing the number of unnecessary write cycles to the device. The memory device includes blocks, pages contained by each of the blocks, and a page abstraction layer containing a look-up table for translating logical page numbers into physical page numbers. A certain number of the pages in at least one of the blocks is preferably reserved so as not to be used in default data storage mode but instead used to shuffle data within the at least one block using a dynamic page address scheme, whereby data are dynamically moved from one page to an empty page in the same block using dynamic page mapping.
摘要翻译：一种基于NAND的闪速存储器件及其操作方法，通过减少对器件的不必要的写入周期的数量来延长器件的使用寿命。存储器件包括块，由每个块包含的页面，以及包含用于将逻辑页码翻译成物理页码的查找表的页面抽象层。优选地，保留至少一个块中的一些页面，以便不在默认数据存储模式中使用，而是使用动态页面地址方案来混洗至少一个块内的数据，由此数据是动态的使用动态页面映射在同一个块中从一个页面移动到一个空页面。

52. 发明授权

US08295529B2 Gaming headset with integrated microphone and adapted for olfactory stimulation 失效
标题翻译：具有集成麦克风的游戏耳机，适用于嗅觉刺激
公开(公告)号：US08295529B2
公开(公告)日：2012-10-23
申请号：US11845896
申请日：2007-08-28
申请人： Ryan M. Petersen , Franz Michael Schuette
发明人： Ryan M. Petersen , Franz Michael Schuette
IPC分类号： H04R25/00
CPC分类号： H04R1/083 , H04R1/028
摘要： A gaming headset adapted for precise delivery of chemical substances capable of olfactory stimulation, such as odorants, fragrances, pheromones, etc. The headset includes at least one earpiece containing a speaker, a feature for securing the earpiece to the person's head while positioning the speaker over one of the person's ears when the headset is worn, an armature disposed relative to the earpiece so as to extend toward the person's mouth, a microphone located on the armature so as to be located in front of the person's mouth, and a feature supported by and extending along the armature for delivering at least one chemical substance to the person's nostril's when the headset is worn.
摘要翻译：适用于精确输送能够嗅觉刺激的化学物质的游戏耳机，例如气味剂，香料，信息素等。头戴式耳机包括至少一个包含扬声器的耳塞，用于将耳机固定到人的头部并将扬声器定位的特征在耳机佩戴时超过人的耳朵之一，相对于耳机设置的电枢朝向人的嘴部延伸，位于电枢上的麦克风位于人的嘴前面，并且支撑的特征沿着衔铁延伸并在耳机佩戴时将至少一种化学物质递送到人的鼻孔。

53. 发明申请

US20120151242A1 APPARATUS FOR OPTIMIZING SUPPLY POWER OF A COMPUTER COMPONENT AND METHODS THEREFOR 审中-公开
标题翻译：用于优化计算机组件的供电能力的装置及其方法
公开(公告)号：US20120151242A1
公开(公告)日：2012-06-14
申请号：US13159557
申请日：2011-06-14
申请人： Timothy P. McGrath , Robert Roark , Franz Michael Schuette
发明人： Timothy P. McGrath , Robert Roark , Franz Michael Schuette
IPC分类号： G06F1/28
CPC分类号： G06F11/3062 , G06F11/3024
摘要： A system and method for monitoring power consumption of a computer system component, such as a central processing unit (CPU), of a desktop computer system. The component is supplied with supply power from a power supply unit of the computer through a power supply cable. A coupling is disposed between the power supply unit and a substrate (e.g., motherboard) on which the component is mounted, and is electrically connected to at least one power supply line of the power supply cable and a power supply connector on the substrate. The power supply line carries a supply voltage. The current flow through the power supply line is determined, a power consumption reading for the component is generated based on the supply voltage and the current flow through the power supply line, and the supply voltage on the power supply line is modulated to determine a lowest current flow therethrough.
摘要翻译：一种用于监视台式计算机系统的计算机系统组件（例如中央处理单元（CPU））的功率消耗的系统和方法。该组件通过电源电缆从计算机的电源单元提供电源。耦合器设置在电源单元和其上安装有组件的基板（例如，主板）之间，并且电连接到电源电缆的至少一个电源线和基板上的电源连接器。电源线承载电源电压。确定通过电源线的电流，基于电源电压和通过电源线的电流产生组件的功耗读数，并且调节电源线上的电源电压以确定最低电流流经其中。

54. 发明授权

US08164935B2 Memory modules and methods for modifying memory subsystem performance 有权
标题翻译：用于修改内存子系统性能的内存模块和方法
公开(公告)号：US08164935B2
公开(公告)日：2012-04-24
申请号：US12632176
申请日：2009-12-07
申请人： Franz Michael Schuette , William J. Allen
发明人： Franz Michael Schuette , William J. Allen
IPC分类号： G11C5/02 , G11C17/18
CPC分类号： G11C5/063 , G11C5/04 , G11C5/14 , H05K1/0262 , H05K1/117 , H05K2201/093 , H05K2201/09663 , H05K2201/10159
摘要： Methods and memory modules adapted for use in computer systems to generate different voltages for core supply (VDD) and input/output supply (VDDQ) inputs to memory components of the computer memory subsystem. The memory module includes a substrate with an edge connector, a memory component, and first and second voltage planes adapted to supply the core supply voltage and the input/output supply voltage to the memory component. The first voltage plane receives a system input voltage from the edge connector, and the second voltage plane is connected to the first voltage plane to receive a second voltage that is either higher or lower than the system input voltage. One of the first and second voltage planes is connected to the memory component to supply the core supply voltage thereto, and the other voltage plane supplies the input/output supply voltage to the memory component.
摘要翻译：适用于计算机系统的方法和存储器模块，用于为计算机存储器子系统的存储器组件产生用于核心电源（VDD）和输入/输出电源（VDDQ）输入的不同电压。存储器模块包括具有边缘连接器的基板，存储器部件以及适于将核心电源电压和输入/输出电源电压提供给存储器部件的第一和第二电压平面。第一电压平面从边缘连接器接收系统输入电压，并且第二电压平面连接到第一电压平面以接收高于或低于系统输入电压的第二电压。第一和第二电压平面中的一个连接到存储器组件以向其提供核心电源电压，而另一个电压平面将输入/输出电源电压提供给存储器组件。

55. 发明申请

US20110258355A1 MODULAR MASS STORAGE DEVICES AND METHODS OF USING 审中-公开
标题翻译：模块化储存设备及其使用方法
公开(公告)号：US20110258355A1
公开(公告)日：2011-10-20
申请号：US12903260
申请日：2010-10-13
申请人： Franz Michael Schuette
发明人： Franz Michael Schuette
IPC分类号： G06F13/00
CPC分类号： G06F3/0632 , G06F3/0607 , G06F3/0679
摘要： A modular mass storage device suitable for use with computers and other processing apparatuses. The mass storage device includes a controller board having a system interface connector, a memory controller, a cache device, and a second connector. The mass storage device further includes a daughter board having at least one non-volatile memory device for data storage, a read-only memory device containing firmware of the mass storage device, and a daughter board connector configured to mate with the second connector of the controller board and thereby form command, address and data paths between the memory controller and the memory device of the daughter board. The memory controller and the memory device are configured so that the memory controller reads the firmware of the read-only memory device when the daughter board connector is mated with the second connector of the controller board.
摘要翻译：适用于计算机和其他处理设备的模块化海量存储设备。大容量存储设备包括具有系统接口连接器，存储器控制器，高速缓存设备和第二连接器的控制器板。大容量存储装置还包括具有用于数据存储的至少一个非易失性存储装置的子板，包含大容量存储装置的固件的只读存储装置和被配置为与第二连接器配对的子板连接器从而在存储器控制器和子板的存储器件之间形成命令，地址和数据路径。存储器控制器和存储器件被配置为使得当子板连接器与控制器板的第二连接器配合时，存储器控制器读取只读存储器件的固件。

56. 发明申请

US20110102997A1 MASS STORAGE DEVICE AND METHOD OF ACCESSING MEMORY DEVICES THEREOF 审中-公开
标题翻译：大容量存储装置及其存取装置的访问方法
公开(公告)号：US20110102997A1
公开(公告)日：2011-05-05
申请号：US12917641
申请日：2010-11-02
申请人： Franz Michael Schuette
发明人： Franz Michael Schuette
IPC分类号： G06F1/16 , H05K7/00
CPC分类号： G06F11/0793 , G06F11/0727 , G06F11/0745
摘要： A mass storage device configured to enable accessing of an array of solid-state memory devices on the storage device in the event of a memory controller failure on the storage device. The storage device includes a printed circuit board, an array of non-volatile solid-state memory devices on the printed circuit board, a system interface connector on the printed circuit board and adapted to connect the mass storage device to a host system, and an onboard memory controller on the printed circuit board and adapted to communicate between the host system and the memory devices. The mass storage device further includes an auxiliary connector on the printed circuit board that is separate from and in addition to the system interface connector. The auxiliary connector provides a direct path for accessing the memory devices that is separate from the onboard memory controller.
摘要翻译：一种大容量存储设备，被配置为在所述存储设备上的存储器控制器故障的情况下，使能够访问所述存储设备上的固态存储器设备的阵列。存储装置包括印刷电路板，印刷电路板上的非易失性固态存储器阵列阵列，印刷电路板上的系统接口连接器，并适于将大容量存储装置连接到主机系统，以及印刷电路板上的板载存储器控制器，并且适于在主机系统和存储器件之间进行通信。大容量存储装置还包括在印刷电路板上的与系统接口连接器分离并且除了系统接口连接器之外的辅助连接器。辅助连接器提供用于访问与板载存储器控制器分离的存储器件的直接路径。

57. 发明申请

US20100312953A1 METHOD AND APPARATUS FOR REDUCING WRITE CYCLES IN NAND-BASED FLASH MEMORY DEVICES 有权
标题翻译：用于减少基于NAND的闪速存储器件中的写入循环的方法和装置
公开(公告)号：US20100312953A1
公开(公告)日：2010-12-09
申请号：US12793023
申请日：2010-06-03
申请人： William J. Allen , Franz Michael Schuette
发明人： William J. Allen , Franz Michael Schuette
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： A NAND-based flash memory device and a method of its operation that extends the life of the device by reducing the number of unnecessary write cycles to the device. The memory device includes blocks, pages contained by each of the blocks, and a page abstraction layer containing a look-up table for translating logical page numbers into physical page numbers. A certain number of the pages in at least one of the blocks is preferably reserved so as not to be used in default data storage mode but instead used to shuffle data within the at least one block using a dynamic page address scheme, whereby data are dynamically moved from one page to an empty page in the same block using dynamic page mapping.
摘要翻译：一种基于NAND的闪速存储器件及其操作方法，通过减少对器件的不必要的写入周期的数量来延长器件的使用寿命。存储器件包括块，由每个块包含的页面，以及包含用于将逻辑页码翻译成物理页码的查找表的页面抽象层。优选地，保留至少一个块中的一些页面，以便不在默认数据存储模式中使用，而是使用动态页面地址方案来混洗至少一个块内的数据，由此数据是动态的使用动态页面映射在同一个块中从一个页面移动到一个空页面。

58. 发明授权

US07738252B2 Method and apparatus for thermal management of computer memory modules 有权
标题翻译：计算机内存模块热管理方法和装置
公开(公告)号：US07738252B2
公开(公告)日：2010-06-15
申请号：US11621396
申请日：2007-01-09
申请人： Franz Michael Schuette , Ryan M. Petersen , Eric L. Nelson , Bhulinder Sethi
发明人： Franz Michael Schuette , Ryan M. Petersen , Eric L. Nelson , Bhulinder Sethi
IPC分类号： H05K7/20 , G06F1/20
CPC分类号： G06F1/206
摘要： A heat spreader and method for thermal management of a computer memory module by promoting natural convection cooling of the memory module. The heat spreader includes a frame surrounding a planar body adapted to be mounted to a memory module of a computer, and a grid defined in the planar body by a plurality of uniformly distributed perforations. The perforations extend through the planar body to allow natural convention between an interior space beneath the planar body and an exterior space above the planar body.
摘要翻译：一种用于通过促进存储器模块的自然对流冷却来对计算机存储器模块进行热管理的散热器和方法。散热器包括围绕适于安装到计算机的存储器模块的平面主体的框架，以及通过多个均匀分布的穿孔限定在平面主体中的格栅。穿孔延伸穿过平面体，以允许平面体下面的内部空间与平面体上方的外部空间之间的自然约定。

59. 发明申请

US20080222349A1 IEEE 1394 INTERFACE-BASED FLASH DRIVE USING MULTILEVEL CELL FLASH MEMORY DEVICES 审中-公开
标题翻译： IEEE 1394基于接口的闪存驱动器，使用多单元电池闪存存储器件
公开(公告)号：US20080222349A1
公开(公告)日：2008-09-11
申请号：US12043628
申请日：2008-03-06
申请人： Jong Kook Lee , Franz Michael Schuette
发明人： Jong Kook Lee , Franz Michael Schuette
IPC分类号： G06F12/00
CPC分类号： G06F13/385 , G11C11/5621
摘要： A flash drive and method of transferring data from a system to a flash drive. The flash drive includes a casing, a plurality of flash memory devices within the casing, each of the flash memory devices having multilevel cells, an IEEE 1394 interface controller within the casing, coupled to the flash memory devices, and interfacing with the flash memory devices for interleaved multichannel access to and from at least two of the flash memory devices, and at least one IEEE 1394 interface connector projecting from the casing for interfacing the flash memory devices with a system through the controller. The method entails coupling a plurality of multilevel cell flash memory devices to a system through an IEEE 1394 interface controller and at least one IEEE 1394 interface connector, and performing interleaved multichannel access to and from at least two of the flash memory devices.
摘要翻译：闪存驱动器和将数据从系统传输到闪存驱动器的方法。闪存驱动器包括壳体，壳体内的多个闪存器件，每个闪存器件具有多电平单元，壳体内的IEEE 1394接口控制器，耦合到闪存器件，并与闪存器件接口用于对来自至少两个闪存器件的交织多通道访问，以及从壳体突出的至少一个IEEE 1394接口连接器，用于通过控制器将闪存器件与系统接口连接。该方法需要通过IEEE 1394接口控制器和至少一个IEEE 1394接口连接器将多个多电平单元闪存器件耦合到系统，并且执行至少两个闪存器件的交错多通道访问。

60. 发明授权

US08910002B2 NAND flash-based storage device with built-in test-ahead for failure anticipation 有权
标题翻译：基于NAND闪存的存储设备，内置测试失败预测
公开(公告)号：US08910002B2
公开(公告)日：2014-12-09
申请号：US12862176
申请日：2010-08-24
申请人： Franz Michael Schuette
发明人： Franz Michael Schuette
IPC分类号： G11C29/12 , G11C16/34 , G11C5/04 , G11C16/04 , G11C29/46 , G11C29/52 , G11C29/04
CPC分类号： G11C16/349 , G11C5/04 , G11C16/04 , G11C29/46 , G11C29/52 , G11C2029/0409 , G11C2029/0411
摘要： A test-ahead feature for non-volatile memory-based mass storage devices to anticipate device failure. The test-ahead feature includes a method performed with a solid-state mass storage device having a controller, a cache memory, and at least one non-volatile memory device. At least a first block is reserved on the at least one non-volatile memory device as a wear-indicator block and a plurality of second blocks are used for data storage. Information is stored corresponding to the number of write and erase cycles encountered by the second blocks during usage of the mass storage device, and the information is accessed to perform wear leveling among the second blocks. The wear-indicator blocks are subjected to an offset number of write and erase cycles in excess of the number of write and erase cycles encountered by the second blocks, after which an integrity check of the first block is performed.
摘要翻译：用于基于非易失性存储器的大容量存储设备的预测功能，用于预测设备故障。测试前景功能包括使用具有控制器，高速缓冲存储器和至少一个非易失性存储器设备的固态大容量存储设备执行的方法。在至少一个非易失性存储器装置上至少保留第一块作为磨损指示符块，并且多个第二块用于数据存储。在使用大容量存储装置期间，信息被存储对应于第二块所遇到的写入和擦除周期的数量，并且访问该信息以在第二块之间执行损耗均衡。损耗指示器块经受超过第二块所遇到的写入和擦除周期数量的写入和擦除周期的偏移量，之后执行第一块的完整性检查。

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