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51. 发明公开

EP1883104A1 Method for manufacturing bonded SOI wafer and bonded SOI wafer manufactured thereby 有权
标题翻译： Verfahren zur Herstellung eines gebundenen SOI-Wafers
公开(公告)号：EP1883104A1
公开(公告)日：2008-01-30
申请号：EP07014401.9
申请日：2007-07-23
申请人： SUMCO Corporation
发明人： Ikeda, Yasunobu , Tomita, Shinichi , Miyahara, Hiroyuki
IPC分类号： H01L21/322 , H01L21/762
CPC分类号： H01L21/02052 , H01L21/3226 , H01L21/76256
摘要： A bonded SOI wafer is manufactured by performing bonding in a state where organics exist on a surface of an active layer wafer and/or on a surface of a supporting wafer and performing heat-treating for bonding reinforcement in a state where the organics are trapped at an interface between the active layer wafer and the supporting wafer to form crystal defects at an interface between the active layer wafer and the oxide film and/or at an interface between the supporting wafer and the oxide film. This allows a simple and inexpensive gettering source to be formed at the interface between an SOI layer and an insulating layer (oxide film). Also, the bonded SOI wafer of the present invention that is manufactured by this method can effectively remove heavy-metal impurities that may have a negative impact on the characteristics of the device and/or the withstand voltage characteristics of the oxide film. Therefore, the manufacturing method and the bonded SOI wafer according to the present invention can be utilized widely as an SOI wafer with improved device characteristics or as a manufacturing method thereof.
摘要翻译：通过在有源层晶片的表面和/或支撑晶片的表面上存在有机物的状态下进行结合，并且在有机物被捕获的状态下进行接合强化的热处理来制造接合的SOI晶片活性层晶片和支撑晶片之间的界面，以在有源层晶片和氧化物膜之间的界面处和/或在支撑晶片和氧化物膜之间的界面处形成晶体缺陷。这允许在SOI层和绝缘层（氧化物膜）之间的界面处形成简单且廉价的吸气源。此外，通过该方法制造的本发明的接合SOI晶片可以有效地去除可能对器件特性和/或耐电压特性产生负面影响的重金属杂质。因此，根据本发明的制造方法和接合SOI晶片可以广泛地用作具有改进的器件特性的SOI晶片或其制造方法。

52. 发明公开

EP1881528A1 Method for producing bonded wafer 审中-公开
标题翻译：生产键合晶圆的方法
公开(公告)号：EP1881528A1
公开(公告)日：2008-01-23
申请号：EP07014349.0
申请日：2007-07-20
申请人： SUMCO Corporation
发明人： Okuda, Hidehiko , Kusaba, Tatsumi
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： A bonded wafer is produced by a method comprising a step of implanting ions of a light element such as hydrogen, helium or the like into a wafer for active layer at a predetermined depth position to form an ion implanted layer, a step of bonding the wafer for active layer to a wafer for support substrate through an insulating film, a step of exfoliating the wafer at the ion implanted layer, a first heat treatment step of conducting a sacrificial oxidation for reducing damage on a surface of an active layer exposed through the exfoliation and a second heat treatment step of raising a bonding strength, in which the second heat treatment step is continuously conducted after the first heat treatment step without removing an oxide film formed on the surface of the active layer.
摘要翻译：贴合晶片通过包括以下步骤的方法制造：在预定深度位置处将诸如氢，氦等的轻元素的离子注入到用于有源层的晶片中以形成离子注入层，将晶片用于通过绝缘膜将用于有源层的有源层连接到用于支撑衬底的晶片;剥离离子注入层处的晶片的步骤;进行牺牲氧化的第一热处理步骤，以减少通过剥离暴露的有源层的表面上的损伤以及提高结合强度的第二热处理步骤，其中在第一热处理步骤之后连续进行第二热处理步骤而不去除形成在有源层表面上的氧化膜。

53. 发明公开

EP1881093A2 Silicon single crystal wafer for IGBT and method for manufacturing silicon single crystal wafer for IGBT 有权
标题翻译：对于用于制造单晶硅晶片用于IGBT的IGBT和方法型结晶硅晶片
公开(公告)号：EP1881093A2
公开(公告)日：2008-01-23
申请号：EP07003441.8
申请日：2007-02-19
申请人： SUMCO CORPORATION
发明人： Ono, Toshiaki , Umeno, Shigeru , Sugimura, Wataru , Hourai, Masataka
IPC分类号： C30B15/00 , C30B29/06
CPC分类号： C30B15/00 , C30B29/06 , H01L21/261
摘要： In this silicon single crystal wafer for IGBT, COP defects and dislocation clusters are eliminated from the entire region in the radial direction of the crystal, the interstitial oxygen concentration is 8.5 × 10 17 atoms/cm 3 or less, and variation in resistivity within the wafer surface is 5% or less. This method for manufacturing a silicon single crystal wafer for IGBT includes introducing a hydrogen atom-containing substance into an atmospheric gas at a hydrogen gas equivalent partial pressure of 40 to 400 Pa, and growing a single crystal having an interstitial oxygen concentration of 8.5 × 10 17 atoms/cm 3 or less at a silicon single crystal pulling speed enabling pulling of a silicon single crystal free of grown-in defects. The pulled silicon single crystal is irradiated with neutrons so as to dope with phosphorous; or an n-type dopant is added to the silicon melt; or phosphorous is added to the silicon melt so that the phosphorous concentration in the silicon single crystal is 2.9 × 10 13 to 2.9 × 10 15 atoms/cm 3 and a p-type dopant having a segregation coefficient smaller than that of the phosphorous is added to the silicon melt so that the concentration in the silicon single crystals is 1 × 10 13 to 1 × 10 15 atoms/cm 3 corresponding to the segregation coefficient thereof.
摘要翻译：在用于IGBT此单晶硅晶片，COP缺陷和位错簇在晶体的径向方向从整个区域消除时，晶格间氧浓度为8.5×10 17原子/ cm 3以下，且变化的电阻率中的晶片表面为5％或更小。这个用于制造IGBT的单晶硅晶片的方法包括：在气氛气体在40至400 Pa的氢气等效分压引入含氢原子的物质引入，并生长单晶具有在8.5×10间隙氧浓度 17原子/ cm 3以下在硅单晶拉制速度使自由生长缺陷的硅单晶提拉。提拉硅单晶用中子照射，用磷掺杂; 或n型掺杂剂被添加到硅熔体; 或磷被添加到硅熔体所以没有在硅单晶中的磷浓度为2.9×10 13〜2.9×10 15原子/厘米3，并且具有一个偏析系数比磷更小的p型掺杂剂添加与硅熔体所以没有在硅单晶的浓度为1×10 13至对应于它们的偏析系数1×10 15原子/厘米3。

54. 发明公开

EP1820603A2 Wafer and method for producing the same 有权
标题翻译： Wafer und Herstellungsverfahrendafür
公开(公告)号：EP1820603A2
公开(公告)日：2007-08-22
申请号：EP07001408.9
申请日：2007-01-23
申请人： SUMCO Corporation
发明人： Morita, Etsurou , Hujie, Kazuo , Ono, Isoroku
IPC分类号： B24B37/04 , B24D3/28
CPC分类号： B24B37/042 , B24D13/147
摘要： A wafer is produced at a step of polishing a predetermined face of a wafer to flatten the predetermined face while supplying a polishing liquid onto a bonded abrasive cloth, wherein the bonded abrasive cloth comprises a urethane bonding material consisting of a soft segment having a polyfunctional isocyanate and a hard segment having a polyfunctional polyol and having an expansion ratio of 1.1-4 times and silica having an average particle size of 0.2-10 µm and a hydroxy group, and has a given ratio of the hard segment occupied in the urethane bonding material, a given volume ratio of silica and a given Shore D hardness.
摘要翻译：在抛光晶片的预定面以平坦化预定面的步骤中制造晶片，同时将抛光液体供给到粘合的研磨布上，其中所述粘结的研磨布包括由具有多官能异氰酸酯的软链段组成的聚氨酯粘结材料具有多官能多元醇的硬链段，其膨胀率为1.1-4倍，平均粒径为0.2〜10μm的二氧化硅和羟基，并且具有在氨基甲酸酯键合材料中占据的硬链段的给定比例，二氧化硅的给定体积比和给定的肖氏D硬度。

55. 发明公开

EP1801863A1 SILICON EPITAXIAL WAFER AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：硅外延晶片及其制造方法
公开(公告)号：EP1801863A1
公开(公告)日：2007-06-27
申请号：EP05781511.0
申请日：2005-08-30
申请人： SUMCO Corporation
发明人： SADAMITSU, Shinsuke c/o SUMCO CORPORATION , HOURAI, Masataka c/o SUMCO CORPORATION
IPC分类号： H01L21/322 , H01L21/205 , H01L27/146
CPC分类号： C30B29/06 , C30B15/00 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/3225 , H01L27/146 , H01L31/186 , Y02P70/521 , Y10T428/265
摘要： A silicon epitaxial wafer of the invention comprises a silicon single crystal wafer sliced from a CZ silicon ingot doped with carbon in a concentration range of not less than 5×10 15 atoms/cm 3 and not more than 5×10 17 atoms/cm 3 and an epitaxial layer consisting of a silicon single crystal epitaxially grown on a front surface of the silicon single crystal wafer. A polycrystalline silicon layer having a thickness of not less than 0.5 µm and not more than 1.5 µm is formed on a back surface of the silicon single crystal wafer.

56. 发明公开

EP1780314A2 Method for manufacturing silicon single crystal 有权
标题翻译： Verfahren zur Herstellung eines Siliciumeinkristalles
公开(公告)号：EP1780314A2
公开(公告)日：2007-05-02
申请号：EP06022359.1
申请日：2006-10-25
申请人： SUMCO CORPORATION
发明人： Furukawa, Jun
IPC分类号： C30B15/20 , C30B29/06
CPC分类号： C30B15/10 , C30B15/20 , C30B29/06 , Y10T117/1004 , Y10T117/1008
摘要： By pulling up an ingot in consideration of deformation of a crucible, generation of the defective ingot is prevented and a plurality of ingots having equivalent quality with the first ingot are pulled up in a multiple pull-up. Firstly, a deformation amount of a crucible for experiment (34) upon melting a silicon raw material and a history of supply power to a heater for experiment (38) are measured to calculate deformation tendency of a crucible for mass production (14). Next, the size of the crucible for mass production is measured, the silicon raw material of the amount equivalent to the amount supplied to the crucible for experiment is melted with a heater for mass production (18), and an initial crucible external position with a predetermined gap (X) is measured before initiating pull-up. Moreover, the deformation amount of the crucible for mass production upon melting the silicon raw material is predicted based on such as a relation between the deformation tendency of the crucible for experiment and the initial crucible external position, an initial crucible internal position when the predetermined gap is provided is predicted based on the deformation amount of the crucible for mass production, and an optimal pulling-up speed of the ingot is derived from predictive calculation to initiate the pull-up of the ingot at the optimal pulling-up speed.
摘要翻译：通过考虑到坩埚的变形而拉起锭，可以防止有缺陷的锭的产生，并且具有与第一锭相同品质的多个锭在多次拉拔中被拉起。首先，测量在硅原料熔化时的实验（34）的坩埚的变形量和实验用加热器（38）的供给历史，计算出批量生产的坩埚的变形趋势（14）。接下来，测量用于批量生产的坩埚的尺寸，将与供给到用于实验的坩埚的量相当的量的硅原料用用于批量生产的加热器（18）熔化，并且将初始坩埚外部位置与在启动上拉之前测量预定间隙（X）。此外，根据实验用坩埚的变形趋势与初始坩埚外部位置之间的关系，预测在原料坩埚熔融时的大规模生产用坩埚的变形量，初始坩埚内部位置基于用于批量生产的坩埚的变形量来预测，并且通过预测计算得出了锭的最佳上拉速度，以最佳上拉速度开始锭的上拉。

57. 发明公开

EP1746639A1 Wet etching method of single wafer 审中-公开
标题翻译： Nassätzverfahreneines einzelnen晶圆
公开(公告)号：EP1746639A1
公开(公告)日：2007-01-24
申请号：EP06014582.8
申请日：2006-07-13
申请人： SUMCO CORPORATION
发明人： Koyata, Sakae, c/o Sumco Corporation , Hashii, Tomohiro, c/o Sumco Corporation , Murayama, Katsuhiko, c/o Sumco Corporation , Takaishi, Kazuhige, c/o Sumco Corporation , Katoh, Takeo, c/o Sumco Corporation
IPC分类号： H01L21/306 , H01L21/00
CPC分类号： H01L21/30608 , H01L21/02019 , H01L21/02087 , H01L21/67075 , H01L21/6708
摘要： Local shape collapse of a wafer end portion is suppressed to the minimum level, and a wafer front surface as well as a wafer end portion is uniformly etched while preventing an etchant from flowing to a wafer rear surface.
There is provided an etching method of a single wafer which supplies an etchant onto a wafer front surface in a state where a single wafer having flattened front and rear surfaces is held, and etches the wafer front surface and a front surface side end portion by using a centrifugal force generated by horizontally rotating the wafer. According to this method, the etchant is intermittently supplied onto the front surface of the wafer in twice or more, supply of the etchant is stopped after the etchant for one process is supplied, and the etchant for the next process is supplied after the supplied etchant flows off from the end portion of the wafer.
摘要翻译：将晶片端部的局部形状塌陷抑制到最小水平，并且在防止蚀刻剂流入晶片后表面的同时均匀地蚀刻晶片前表面以及晶片端部。提供了在保持具有平坦的前后表面的单个晶片的状态下将蚀刻剂提供到晶片前表面的状态的单个晶片的蚀刻方法，并且通过使用晶片前表面和前表面侧端部通过水平旋转晶片产生的离心力。根据该方法，蚀刻剂以两次或更多次间歇地供给到晶片的前表面上，在提供一个工艺的蚀刻剂之后停止供应蚀刻剂，并且在所提供的蚀刻剂之后提供用于下一工艺的蚀刻剂从晶片的端部流出。

58. 发明公开

EP1724822A3 Semiconductor substrate and manufacturing method thereof 审中-公开
标题翻译：其制备半导体衬底和处理
公开(公告)号：EP1724822A3
公开(公告)日：2007-01-24
申请号：EP06009879.5
申请日：2006-05-12
申请人： SUMCO Corporation , DENSO CORPORATION
发明人： Nogami, Syouji , Yamaoka, Tomonori , Yamauchi, Shoichi , Yamaguchi, Hitoshi
IPC分类号： H01L21/329 , H01L29/861
CPC分类号： H01L29/861 , H01L29/0634 , H01L29/6609
摘要： In order to suppress deterioration in charge balance and maintain excellent withstand voltage characteristics after forming a super junction structure on a semiconductor substrate, a plurality of columnar first epitaxial layers are respectively formed on a surface of a substrate main body at predetermined intervals, and a plurality of second epitaxial layers are respectively formed in trenches between the plurality of first epitaxial layers. A concentration distribution of a dopant included in the first epitaxial layer in a surface parallel with the surface of the substrate main body is configured to match with a concentration distribution of a dopant included in the second epitaxial layer in a surface parallel with the surface of the substrate main body.

59. 发明公开

EP1734565A1 METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER AND SEMICONDUCTOR WAFER MANUFACTURED BY SUCH METHOD 有权
标题翻译： VERFAHREN ZUR HERSTELLUNG EINES HALBLEITER-WAFERS
公开(公告)号：EP1734565A1
公开(公告)日：2006-12-20
申请号：EP05727725.3
申请日：2005-03-31
申请人： SUMCO Corporation , DENSO CORPORATION
发明人： NOGAMI, S., c/o SUMCO CORPORATION. , HORIOKA, Y., c/o SUMCO CORPORATION. , YAMAUCHI, S., c/o DENSO CORPORATION
IPC分类号： H01L21/205 , H01L21/306
CPC分类号： H01L21/02063 , H01L21/02068 , H01L21/0237 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/2205 , H01L29/0634
摘要： A resistivity of an epitaxial layer in a trench is changed in a stepwise manner by reducing a quantity of an impurity diffused into the epitaxial layer in the trench from a semiconductor wafer in a stepwise manner, thereby suppressing an influence of auto-doping from the semiconductor wafer.
An epitaxial layer 17 is grown in a trench 16 of a semiconductor wafer 10 having a trench structure by gradually reducing a temperature in a temperature in the range of 400 to 1150°C by a vapor growth method while supplying a silane gas as a raw material gas, thereby filling the epitaxial layer 17 in the trench 16.
摘要翻译：沟槽中的外延层的电阻率通过逐步地从半导体晶片减少从沟槽中扩散到外延层中的杂质的量而逐步地改变，从而抑制半导体自动掺杂的影响晶圆。外延层17在具有沟槽结构的半导体晶片10的沟槽16中通过气相生长法逐渐降低400〜1150℃的温度，同时以硅烷气体为原料从而填充沟槽16中的外延层17。

60. 发明公开

EP1726402A1 Wafer polishing apparatus and method for polishing wafers 有权
标题翻译： Vorrichtung und Verfahren zum polieren von Halbleiterscheiben
公开(公告)号：EP1726402A1
公开(公告)日：2006-11-29
申请号：EP06009972.8
申请日：2006-05-15
申请人： SUMCO Corporation
发明人： Hashii, Tomohiro , Murayama, Katsuhiko , Koyata, Sakae , Takaishi, Kazushige
IPC分类号： B24B57/02 , B24B37/04
CPC分类号： B24B37/04 , B24B57/02 , H01L21/02024
摘要： This wafer polishing apparatus includes: a polishing plate having a polishing pad; a carrier plate which is placed facing the polishing pad and which slides and presses wafers against the polishing pad, while rotating in a state of holding the wafers; and an abrasive slurry supply device, wherein the abrasive slurry supply device is able to supply different abrasive slurries, each of the abrasive slurries contains abrasives of which the average grain size is different from those contained in the other abrasive slurries. This method for polishing wafers includes: while supplying an abrasive slurry to a surface of a polishing pad, sliding and pressing wafers against the polishing pad, wherein different abrasive slurries are supplied to the surface of the polishing pad, and each of the abrasive slurries contains abrasives of which the average grain size is different from those contained in the other abrasive slurries.
摘要翻译：该晶片抛光装置包括：具有抛光垫的抛光板; 载体板，其面向抛光垫放置并且在保持晶片的状态下旋转的同时将晶片滑动并压靠在抛光垫上; 和磨料浆料供应装置，其中磨料浆料供应装置能够供应不同的磨料浆料，每个磨料浆料都含有平均粒径与其它磨料浆料中所含磨料不同的研磨剂。抛光晶片的这种方法包括：在将研磨浆料供应到抛光垫的表面的同时，将研磨浆料滑动并压在抛光垫上，其中不同的磨料浆料被供应到抛光垫的表面，并且每个磨料浆料含有其研磨剂的平均粒径与其它磨料浆料中所含的磨粒不同。

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