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51. 发明专利

DE19814415A1 未知
公开(公告)号：DE19814415A1
公开(公告)日：1998-11-12
申请号：DE19814415
申请日：1998-03-31
申请人： QUICKTURN DESIGN SYSTEMS INC A
发明人： SARNO TONY R , SCHAEFER INGO , CHILTON JOHN E , PAPAMARCOS MARK S , CHAN BERNARD Y , TSOU MICHAEL C
IPC分类号： G06F17/50 , G06F11/25 , G06F11/26 , G06F11/34 , G06F9/455 , G01R31/3177
摘要： A logic analysis subsystem in a time-sliced emulator. The logic analysis subsystem "reconstructs" signals that were previously reduced by the compiler and allows the user to set breakpoints and triggers using these and other signals of the emulated circuit. The present invention includes a "logic analysis subsystem compiler" and "logic analysis subsystem hardware." The logic analysis subsystem compiler is either a subpart of the regular emulator compiler or is a standalone compiler. It compiles the design to be emulated and generates control instructions for the logic analysis subsystem hardware. The logic analysis subsystem hardware is incorporated into the time-sliced emulator to receive signals generated by the emulator during emulation. When the logic analysis subsystem operates, the control instructions cause the logic analysis subsystem to reconstruct previously reduced signals received from the emulator. These signals (along with the signals received from the emulator) may be used by the user to set breakpoints and triggers in the logic analysis subsystem.

52. 发明专利

GB2324626A Software reconfigurable target I/O in a circuit emulation system 未知
公开(公告)号：GB2324626A
公开(公告)日：1998-10-28
申请号：GB9804371
申请日：1998-03-02
申请人： QUICKTURN DESIGN SYSTEMS INC
发明人： SARNO TONY R , SCHAEFER INGO , CHILTON JOHN E , PAPAMARCOS MARK S , BLANDING CURTIS J
IPC分类号： G06F11/22 , G06F11/26 , G06F17/50
摘要： A time-sliced hardware-based emulator can include; programmable I/O assignment; programmable levels of DC voltage; programmable pull-up or pull-down resistors in the emulator on a pin-by pin basis; programmable forcing and/or disabling of value output from the emulator on each pin; programmable clocking; and programmable sample modes. An emulator 102 is connected to a target system 110 via Pod System Interfaces(PSI) 104, specially designed cable 106, and Pod User Interfaces(PUI) 108. For data traveling from the emulator to the target system, each PSI receives up to 128 bits of data from the emulator, and also output enable bits. Each cable, however, is only 32 bits wide. Therefore, the emulator multiplexes the data sent over the cable, sending eight interleaved groups of 32 bits to the PSI in accordance with a fast clock signal. Each PUI receives the groups of 32 bits from the PSI and sends them to the target system in accordance with control signals from the emulator. For data traveling from the target system to the emulator, each PUI receives up to 128 bits of data from the target system. Each PUI sends four groups of 32 bits in accordance with a fast clock signal. Each PSI receives the groups of 32 bits and holds them in an internal register, sending the received bits to the emulator under control of the emulator.

53. 发明专利

GB9806058D0 Logic analysis subsystem in a time-sliced emulator 未知
公开(公告)号：GB9806058D0
公开(公告)日：1998-05-20
申请号：GB9806058
申请日：1998-03-20
申请人： QUICKTURN DESIGN SYSTEMS INC
IPC分类号： G06F17/50 , G06F11/25 , G06F11/26 , G06F11/34
摘要： A logic analysis subsystem in a time-sliced emulator. The logic analysis subsystem "reconstructs" signals that were previously reduced by the compiler and allows the user to set breakpoints and triggers using these and other signals of the emulated circuit. The present invention includes a "logic analysis subsystem compiler" and "logic analysis subsystem hardware." The logic analysis subsystem compiler is either a subpart of the regular emulator compiler or is a standalone compiler. It compiles the design to be emulated and generates control instructions for the logic analysis subsystem hardware. The logic analysis subsystem hardware is incorporated into the time-sliced emulator to receive signals generated by the emulator during emulation. When the logic analysis subsystem operates, the control instructions cause the logic analysis subsystem to reconstruct previously reduced signals received from the emulator. These signals (along with the signals received from the emulator) may be used by the user to set breakpoints and triggers in the logic analysis subsystem.

54. 发明专利

DE69221632D1 未知
公开(公告)号：DE69221632D1
公开(公告)日：1997-09-18
申请号：DE69221632
申请日：1992-10-29
申请人： CUBE INC I , QUICKTURN DESIGN SYSTEMS INC
发明人： JENQ YIH-CHYUN , LOFSTROM KEITH , HUANG THOMAS B
IPC分类号： H03K19/0175 , H03K5/02 , H04L5/16 , H03K17/16
摘要： A bi-directional bus repeater includes two unidirectional bus repeaters connected for retransmitting signals in opposite directions between two buses. When an external bus driver pulls either bus low, one of the unidirectional bus repeaters pulls the other bus low. When the external bus driver allows the bus to rise to the high logic level, the unidirectional bus repeater temporarily supplies a high charging current to the other bus to quickly pull it up. Each unidirectional bus repeater also generates signals indicating when it is actively pulling its output bus up or down and the indicating signals inhibit one unidirectional bus repeater from actively driving its output when the other unidirectional bus repeater is actively driving its output.

55. 发明专利

GB2287810A Multi-port memory emulation using tag registers 未知
公开(公告)号：GB2287810A
公开(公告)日：1995-09-27
申请号：GB9505638
申请日：1995-03-21
申请人： QUICKTURN DESIGN SYSTEMS INC
发明人： HUANG THOMAS B
IPC分类号： G11C11/401 , G06F17/50 , G11C8/16 , G11C7/00 , G06F12/00
摘要： A method of implementing a multi-port memory circuit in the memory resources of configuration logic blocks of programmable logic devices. The multi-port memory circuit to be implemented comprises a memory array having memory locations for storing data, read ports for reading data from the memory array and write ports for writing data to the memory array. Multiple duplications of the memory array are created in order to implement as many read ports and write ports as the multi-port memory circuit being implemented. The memory locations within the duplicate memory arrays are tagged to indicate which memory location had data written therein last so that only the last written data will be read through the various read ports.

56. 发明专利

DE69737757D1 未知
公开(公告)号：DE69737757D1
公开(公告)日：2007-07-12
申请号：DE69737757
申请日：1997-02-05
申请人： QUICKTURN DESIGN SYSTEMS INC
发明人： CHILTON JOHN E , SARNO TONY R , SCHAEFER INGO
IPC分类号： G06F11/22 , G06F11/26 , G06F17/50
摘要： A system and method for emulating memory designs (195) is described. The system includes a time sliced logic emulator (150). The time sliced logic emulator (150) emulates the functions performed in one cycle of a target design by emulating portions of the functions in a set of time slices. That is, a set of time slices represents a single clock cycle in the target design. The system emulates many different types of memory designs (195) included in the target design. The system includes an emulation memory (180). The memory designs (195) are mapped to the emulation memory (180) via a programmable address generation block. For a given time slice, the programmable address generation block generates an address that maps all or part of a memory design address to an emulation memory address. The programmable address generation block allows multiple memory designs to be mapped to a single emulation memory and allows a single memory design to be mapped to multiple emulation memories. Thus over multiple time slices, the system can emulate many different types of memories.

57. 发明专利

CA2218458C METHOD AND APPARATUS FOR DESIGN VERIFICATION USING EMULATIONAND SIMULATION 未知
公开(公告)号：CA2218458C
公开(公告)日：2005-12-06
申请号：CA2218458
申请日：1997-10-16
申请人： QUICKTURN DESIGN SYSTEMS INC
发明人： BERSHTEVN MIKHAIL , SAMPLE STEPHEN P
IPC分类号： G01R31/28 , G06F11/22 , G06F11/26 , G06F17/50
摘要： A method and apparatus for combining emulation and simulation of a logi c design. The method and apparatus can be used with a logic design that includ es gate-level descriptions, behavioral representations, structural representations, or a combination thereof. The emulation and simulation portions are combined in a manner that minimize s the time for transferring data between the two portions. Simulation is performed by one o r more microprocessors while emulation is performed in reconfigurable hardware such as field programmable gate arrays. When multiple microprocessors are employed, independent portions of the logic design are selected to be executed on the multiple synchronized microprocessors. Reconfigurable hardware also performs event detecting and scheduling operations to aid the simulation, and to reduce processing time.

58. 发明专利

DE68929518D1 未知
公开(公告)号：DE68929518D1
公开(公告)日：2004-06-03
申请号：DE68929518
申请日：1989-10-04
申请人： QUICKTURN DESIGN SYSTEMS INC
发明人： BUTTS MICHAEL R , BATCHELLER JON A
IPC分类号： G01R31/28 , G06F11/22 , G06F11/25 , G06F15/78 , G06F17/50 , H01L21/82 , H03K19/173 , H03K19/177 , G06F17/60
摘要： A method is claimed for stimulating a functional circuit with logical stimulus, in order to determine the response of the functional circuit to that logical stimulus. The claimed method comprises the steps of (a) configuring a reconfigurable logic apparatus to implement the functional circuit, said reconfigurable logic apparatus comprising N reprogrammable logic devices, where N is a number greater than one, said N reprogrammable logic devices being interconnected by reprogrammable interconnect devices, and said functional circuit being implemented by at least two of said N reprogrammable logic devices; (b) converting the logical stimulus into input electrical signals; (c) inputting said electrical signals to said N reconfigurable logic apparatus which is configured with the functional circuit; and (d) receiving output electrical signals from said reconfigurable logic apparatus; and (e) converting said output electrical signals into software form. Also claimed are methods of simulating a functional circuit design, and a method of simulating digital logic networks.

59. 发明专利

AT225058T 未知
公开(公告)号：AT225058T
公开(公告)日：2002-10-15
申请号：AT98923498
申请日：1998-05-18
申请人： QUICKTURN DESIGN SYSTEMS INC
发明人： SAMPLE STEPHEN P , BERSHTEYN MIKHAIL , BUTTS MICHAEL R
IPC分类号： G01R31/28 , G01R31/317 , G06F11/22 , G06F11/26 , G06F17/50 , G06F11/25

60. 发明专利

GB2325317B Logic analysis subsystem in a time-sliced emulator 未知
公开(公告)号：GB2325317B
公开(公告)日：2002-04-17
申请号：GB9806058
申请日：1998-03-20
申请人： QUICKTURN DESIGN SYSTEMS INC
发明人： SARNO TONY R , SCHAEFER INGO , CHILTON JOHN E , PAPAMARCOS MARK S , CHAN BERNARD Y , TSOU MICHAEL C
IPC分类号： G06F17/50 , G06F11/25 , G06F11/26 , G06F11/34
摘要： A logic analysis subsystem in a time-sliced emulator. The logic analysis subsystem "reconstructs" signals that were previously reduced by the compiler and allows the user to set breakpoints and triggers using these and other signals of the emulated circuit. The present invention includes a "logic analysis subsystem compiler" and "logic analysis subsystem hardware." The logic analysis subsystem compiler is either a subpart of the regular emulator compiler or is a standalone compiler. It compiles the design to be emulated and generates control instructions for the logic analysis subsystem hardware. The logic analysis subsystem hardware is incorporated into the time-sliced emulator to receive signals generated by the emulator during emulation. When the logic analysis subsystem operates, the control instructions cause the logic analysis subsystem to reconstruct previously reduced signals received from the emulator. These signals (along with the signals received from the emulator) may be used by the user to set breakpoints and triggers in the logic analysis subsystem.

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