专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明专利

JP3449964B2 失效
公开(公告)号：JP3449964B2
公开(公告)日：2003-09-22
申请号：JP2000140758
申请日：2000-05-12
IPC分类号： H04B15/00 , H04B3/18 , H04B15/02 , H04L27/00

42. 发明专利

JP3246443B2 失效
公开(公告)号：JP3246443B2
公开(公告)日：2002-01-15
申请号：JP14696798
申请日：1998-05-28
IPC分类号： G06F3/00 , G06F13/40 , G11C11/401 , H03K19/0175 , H04B3/18 , H04L25/02

43. 发明专利

JP2001211105A METHOD AND DEVICE FOR ECHO CANCELATION 失效
公开(公告)号：JP2001211105A
公开(公告)日：2001-08-03
申请号：JP2000357073
申请日：2000-11-24
申请人： CIT ALCATEL
发明人： VANDERBAUWHEDE WIM , BOXHO JEAN , MACQ DAMIEN LUC FRANCOIS
IPC分类号： H04B3/20 , H03H7/00 , H04B20060101 , H04B1/58 , H04B3/03 , H04B3/18 , H04B3/23 , H04L27/01 , H04M1/58 , H04M9/08 , H04Q3/42
摘要： PROBLEM TO BE SOLVED: To provide a method and a device for echo cancelation of a communication line system. SOLUTION: The echo cancelation of the communication line system, specially, an ISDN or XDSL system is carried out by an adjustable hybrid circuit 5 which is united to an analog part of a front end 3 and has an adjustable passive element and the value of the adjustable passive element is controlled by a digital control means 4 such as a microprocessor.

44. 发明专利

JP2001007870A NOISE REDUCTION DEVICE 失效
公开(公告)号：JP2001007870A
公开(公告)日：2001-01-12
申请号：JP2000140758
申请日：2000-05-12
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KEI SHINYU
IPC分类号： H04B15/00 , H04B3/18 , H04B15/02 , H04L27/00
摘要： PROBLEM TO BE SOLVED: To minimize a spurious noise by turning on/off transmission power corresponding to an enable signal generated from a control section in response to the noise, eliminating a prescribed noise generated from a programmable gain controller when a modem transmits no signal, tuning the output of a noise elimination signal and outputting the tuned output to a coaxial cable network. SOLUTION: A CPU 21 adjusts a speed of a transmission level of an up- stream through a programmable gain control section 22. In this case, an enable signal supplied from the CPU 21 controls on/off intermission to the programmable gain control section 22. A transformer 23 coverts a controlled transmission level into an another level, which is given to a noise elimination section 24, in which the spurious noise is minimized. A tuner 25 finally tunes the output of the noise elimination section 24 and the output of the tuner 25 is given to a coaxial cable network. In the case that a cable modem transmits no signal, the enable signal from the CPU 21 goes to a low level to reduce the spurious noise.

45. 发明专利

JPH07288438A AGC CIRCUIT FOR RECEIVED SIGNAL 失效
公开(公告)号：JPH07288438A
公开(公告)日：1995-10-31
申请号：JP7721194
申请日：1994-04-15
申请人： FUJITSU LTD
发明人： MORITA MASAYOSHI , KABURAGI KENICHI
IPC分类号： H03G3/30 , H04B3/06 , H04B3/18
摘要： PURPOSE:To provide the AGC circuit for received signal for which circuit scale is reduced and power consumption is decreased by variably amplifying an input signal while using a variable resistor means as a load resistor for changing a resistance value corresponding to a detected voltage. CONSTITUTION:A received input signal IN is inputted to a peak detection circuit 1 and an NchFET 3-2 of an AGC part 3. First of all, the signal IN is detected by the circuit 1, and a peak value Vp at a positive H level is detected with a DC level as a reference. That value Vp is inverted and amplified by an inverting amplifier 2 on the next stage, the negative voltage of the output is inputted to the gate of a PchFET 3-1 at the AGC part 3, and resistance between the drain and source is controlled. The drain of the FET 3-1 is directly connected to the drain of the FET 3-2 for amplifying the signal, operated as its load resistor, DC cut from its direct connecting point by a capacitor C and outputs the change component of an output voltage from the drain of the FET 3-2 corresponding to the change component of the signal IN.

46. 发明专利

JPH077345A VARIABLE EQUALIZING AMPLIFIER 失效
公开(公告)号：JPH077345A
公开(公告)日：1995-01-10
申请号：JP494694
申请日：1994-01-21
申请人： NAT SEMICONDUCTOR CORP
发明人： GEERII DEII PORUHEMASU
IPC分类号： H03F3/45 , H03G3/00 , H03G3/10 , H03H11/48 , H04B3/06 , H04B3/14 , H04B3/18 , H04L25/12
摘要： PURPOSE: To obtain an adaptive equalizing circuit which equalizes a frequency response to the varying length of a transmission line by varying the ratio between an equalized signal and a nonequalized signal which are combined together for forming an equalized output signal. CONSTITUTION: An adaptive equalizing circuit 10 has a boost stage 12 which generates a completely equalized voltage signal Vfe by compensating an input voltage signal Vi with respect to frequency attenuation on the maximum length of a transmission line. A first variable gain stage 14 amplifies the completely equalized voltage signal Vfe and generates an amplified equalized voltage signal Vae in accordance with a first gain control signal Vfg. A second variable gain stage 16 amplifies the input voltage signal Vi and generates an amplified nonequalized voltage signal Vane in accordance with a second gain control signal Vsg. An addition stage 18 generates an equalized output voltage signal Vo by combining the amplified equalized voltage signal Vae and amplified nonequalized voltage signal Vane together. Therefore, a circuit which equalizes a frequency response to the varying length of the transmission line can be obtained.

47. 发明专利

JPS5145207B1 失效
公开(公告)号：JPS5145207B1
公开(公告)日：1976-12-02
申请号：JP1591370
申请日：1970-02-26
IPC分类号： H04N3/12 , H01L27/07 , H03H11/52 , H03K3/02 , H03K5/01 , H04B3/18 , H04L25/20 , H03F3/62 , H03H5/00 , H03K3/05 , H04N3/14

48. 发明专利

JP2012060666A Electric dispersion equivalent circuit 有权
标题翻译：电分散等效电路
公开(公告)号：JP2012060666A
公开(公告)日：2012-03-22
申请号：JP2011249557
申请日：2011-11-15
申请人： Nippon Telegr & Teleph Corp , 日本電信電話株式会社
发明人： ITO TOSHIHIRO , SANO KOICHI , MURATA KOICHI
IPC分类号： H04B3/18 , H04B5/02
摘要： PROBLEM TO BE SOLVED: To provide an electric dispersion equalizer capable of waveform shaping of a high speed signal without making an input signal waveform distorted.SOLUTION: In the case of a tap number 3, for example, between an input buffer 1 and an output buffer 5, differential input signals from each of the input buffer 1 and a first and second delay circuits 21R and 22R which carry out delaying operation successively by prescribed delay time is multiplied by each of specified three tap coefficients a1, a2, and a3 in a first to third multiplier circuit 31 to 33, and each of the results of the multiplication is added successively in a first and second adder circuits 41 and 42R of 2 inputs to be output via the output buffer 5. With respect to at least some circuits of respective circuits of the input buffer 1, the first and second delay circuits 21R and 22R, the first to third multiplier circuits 31 to 33, the first and second adder circuits 41 and 42R, and the output buffer 5, differential pairs included in these circuits are connected directly to differential pairs included in the next stage circuits.
摘要翻译：要解决的问题：提供一种能够在不使输入信号波形失真的情况下对高速信号进行波形整形的电色差均衡器。解决方案：在抽头号3的情况下，例如，在输入缓冲器1和输出缓冲器5之间，来自输入缓冲器1和第一和第二延迟电路21R和22R中的每一个的差分输入信号携带在第一至第三乘法器电路31至33中，依次按规定的延迟时间进行输出延迟运算与规定的三个抽头系数a1，a2，a3中的每一个进行乘法运算，将乘法运算的结果依次加到第一和第二乘法运算器 2个输入的加法电路41和42R经由输出缓冲器5输出。对于输入缓冲器1，第一和第二延迟电路21R和22R的各个电路的至少一些电路，第一至第三乘法器电路31 到33，第一和第二加法器电路41和42R以及输出缓冲器5，包括在这些电路中的差分对直接连接到下一级电路中包括的差分对。版权所有（C）2012，JPO＆INPIT

49. 发明专利

JP4741991B2 Serializer / deserializer system of transfer device 有权
公开(公告)号：JP4741991B2
公开(公告)日：2011-08-10
申请号：JP2006193548
申请日：2006-07-14
申请人：アラクサラネットワークス株式会社 , 株式会社日立製作所
发明人：恵一日下田 , 功木村 , 孝行村中 , 隆武藤 , 康弘藤村 , 淳志馬場
IPC分类号： H04B3/10 , H04B3/04 , H04B3/18 , H04L25/03
CPC分类号： H04L25/0274 , H04L25/0288

50. 发明专利

JP4549745B2 Receiver circuit 有权
公开(公告)号：JP4549745B2
公开(公告)日：2010-09-22
申请号：JP2004173106
申请日：2004-06-10
申请人：学校法人慶應義塾 , 富士通株式会社
发明人：安基富田 , 淳二小川 , 泰孝田村
IPC分类号： H03H11/04 , H04B3/18

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式