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41. 发明公开

EP0283077A1 Dispositif de décodage de signaux codés en duobinaire 失效
标题翻译：装置，用于解码双二进制编码信号。
公开(公告)号：EP0283077A1
公开(公告)日：1988-09-21
申请号：EP88200393.2
申请日：1988-03-02
申请人： LABORATOIRES D'ELECTRONIQUE PHILIPS , Philips Electronics N.V.
发明人： Lamnabhi, Moustanir Société Civile S.P.I.D. , Salembier, Philippe Société Civile S.P.I.D.
IPC分类号： H03M5/16 , H04L25/497
CPC分类号： H04L25/497 , H03M5/16
摘要： Dispositif de décodage des signaux reçus en sortie d'un canal de transmission après codage en duobinaire d'une séquence de signaux numériques binaires, applicable notamment à la réception de signaux de télévision au standard D2-MAC-paquets et caractérisé en ce qu'il comprend : (A) un premier étage de détermination et de construction de chemins binaires, comprenant lui-même (a) trois mémoires de stockage de probabilités conditionnelles respectives P(y/0), P(y/1), P(y/2) adressées en parallèle par le signal y reçu et destinées à recevoir un signal duobinaire déterminé y lorsqu'un signal duobinaire x = 0, 1 ou 2 a été émis ; (b) deux circuits de sélection et de stockage des deux probabilités conditionnelles correspondant aux deux séquences les plus vraisemblables ; (c) un circuit de reconstruction progressive des chemins binaires ainsi sélectionnés et de sélection de celui des deux qui est le plus vraisemblable ; (B) un deuxième étage d'interdiction de dépassement de la capacité de stockage dans lesdits circuits de sélection et de stockage dudit premier étage, constituant une boucle de rétroaction sur les entrées desdits circuits.

42. 发明公开

EP0282249A2 Logic circuit employing field effect transistor having junction with rectifying characteristic between gate and source 失效
标题翻译：一种逻辑电路，与具有栅极和源极之间的整流特性的连接的场效应晶体管。
公开(公告)号：EP0282249A2
公开(公告)日：1988-09-14
申请号：EP88301948.1
申请日：1988-03-07
申请人： FUJITSU LIMITED
发明人： Watanabe, Yuu
IPC分类号： H03M5/16 , H03K19/094 , H03K19/21
CPC分类号： H03M5/16 , H03K19/215
摘要： A logic circuit comprises a first terminal (V DD ) for receiving a first power source voltage, a second terminal (V SS ) for receiving a second power source voltage lower than the first power source voltage, a third terminal (V REF ) for receiving a reference voltage, an input terminal (V IN ) for receiving an input voltage, an output terminal (V OUT ) for outputting an output voltage, a load (R20, Q L ) coupled between the first terminal and the output terminal, and first and second FETs (Tr3, Tr2) coupled in series between the output terminal and the second terminal. The first FET (Tr3) is coupled to the output terminal and has a gate coupled to the third terminal. The second FET (Tr2) is coupled to the second terminal. The second FET has a gate coupled to the input terminal, and has a junction with a rectifying characteristic between the gate and source thereof.
摘要翻译：一种逻辑电路，包括：第一端子（VDD），用于接收第一电源电压，用于接收第二电源电压小于第一电源电压低的第二端子（VSS），第三端子（VREF），用于接收一个参考电压一种用于在输入电压接收到输出端（VOUT）用于开始输出电压，耦合在所述第一端子和所述输出端子，第一和第二FET之间的负载（R20，QL）输出输入端（VIN）（Tr的3 TR2）耦接在所述输出端子与所述第二端子之间。第一FET（Tr3的）耦合到输出端，并且具有耦合到所述第三端子的栅极。第二FET（TR2）被耦合到所述第二端子。第二FET具有耦合到所述输入端子的栅极，与栅极和源极之间与一个整流特性的结。

43. 发明公开

US20230178869A1 DIGITAL ISOLATOR AND DIGITAL SIGNAL TRANSMISSION METHOD THEREOF 审中-公开
公开(公告)号：US20230178869A1
公开(公告)日：2023-06-08
申请号：US18072851
申请日：2022-12-01
申请人： Silergy Semiconductor Technology (Hangzhou) LTD
发明人： Chiqing Wang , Wei Chen , Yufei Dong , Xiaodong Huang , Chen Zhao
IPC分类号： H01P1/36 , H03M5/16
CPC分类号： H01P1/36 , H03M5/16
摘要： A digital isolator can include: an encoding circuit configured to receive an input digital signal, and to encode a rising edge and a falling edge of the input digital signal into different coded signals; an isolating element coupled to encoding circuit, and being configured to transmit the coded signal in an electrical isolation manner; and a decoding circuit configured to receive the coded signal through the isolation element, and to decode the coded signal to obtain the rising edge and the falling edge, in order to output an output digital signal consistent with the input digital signal, where the rising edge of the input digital signal is encoded as a first pulse sequence, and the falling edge of the input digital signal is encoded as a second pulse sequence different from the first pulse sequence.

44. 发明授权

US09686107B2 Methods and systems for chip-to-chip communication with reduced simultaneous switching noise 有权
公开(公告)号：US09686107B2
公开(公告)日：2017-06-20
申请号：US15169446
申请日：2016-05-31
申请人： Kandou Labs, S.A.
发明人： John Fox , Brian Holden , Peter Hunt , John D. Keay , Amin Shokrollahi , Richard Simpson , Anant Singh , Andrew Kevin John Stewart , Giuseppe Surace
IPC分类号： H04L25/49 , H04L25/493 , H04L25/02 , H03M5/16 , H03M5/20 , G06F13/42 , H04L29/06
CPC分类号： H04L25/4906 , G06F13/426 , H03M5/16 , H03M5/20 , H04L25/0272 , H04L25/4917 , H04L25/493 , H04L69/04 , Y02D10/14 , Y02D10/151
摘要： Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.

45. 发明授权

US09124557B2 Methods and systems for chip-to-chip communication with reduced simultaneous switching noise 有权
标题翻译：具有降低同时开关噪声的芯片到芯片通信的方法和系统
公开(公告)号：US09124557B2
公开(公告)日：2015-09-01
申请号：US14158452
申请日：2014-01-17
申请人： Kandou Labs, S.A.
发明人： John Fox , Brian Holden , Peter Hunt , John D. Keay , Amin Shokrollahi , Richard Simpson , Anant Singh , Andrew Kevin John Stewart , Giuseppe Surace
IPC分类号： H03M5/16 , H03M5/20 , H04L29/06 , H04L25/49
CPC分类号： H04L25/4906 , G06F13/426 , H03M5/16 , H03M5/20 , H04L25/0272 , H04L25/4917 , H04L25/493 , H04L69/04 , Y02D10/14 , Y02D10/151
摘要： Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.
摘要翻译：描述了用于通过物理信道传输数据的系统和方法，以提供高速，低延迟的接口，例如在显着减少或消除的同时开关输出噪声的存储器控制器和存储器件之间。公开了这样的信道接口的控制器侧和存储器侧实施例，其不需要额外的引脚数或数据传输周期，具有低功率利用率，并且引入最小的附加等待时间。在本发明的一些实施例中，三个或更多个电压电平用于信令。

46. 发明授权

US09015566B2 Power and pin efficient chip-to-chip communications with common-mode rejection and SSO resilience 有权
标题翻译：电源和引脚高效的芯片到芯片通信，具有共模抑制和SSO弹性
公开(公告)号：US09015566B2
公开(公告)日：2015-04-21
申请号：US14028240
申请日：2013-09-16
申请人： École Polytechnique Fédérale de Lausanne (EPFL)
发明人： Harm Cronie , Amin Shokrollahi
IPC分类号： G06F11/00 , H04L1/00 , H03M5/04 , H03M5/16 , H03M13/31
CPC分类号： H04L1/0041 , H03M5/04 , H03M5/16 , H03M13/31 , H04L1/0057 , H04L2001/0094
摘要： In bus communications methods and apparatus, a first set of physical signals representing the information to be conveyed over the bus is provided, and mapped to a codeword of a spherical code, wherein a codeword is representable as a vector of a plurality of components and the bus uses at least as many signal lines as components of the vector that are used, mapping the codeword to a second set of physical signals, wherein components of the second set of physical signals can have values from a set of component values having at least three distinct values for at least one component, and providing the second set of physical signals for transmission over the data bus in a physical form.
摘要翻译：在总线通信方法和装置中，提供表示要通过总线传送的信息的第一组物理信号，并将其映射到球码的码字，其中码字可表示为多个分量的向量，并且总线使用至少与所使用的向量的分量相同的信号线，将码字映射到第二组物理信号，其中第二组物理信号的分量可以具有来自具有至少三个的组分值的集合的值提供用于至少一个组件的不同值，以及提供第二组物理信号，以便以物理形式在数据总线上传输。

47. 发明授权

US07990292B2 Method for transmission of a digital message from a display to a handheld receiver 有权
标题翻译：将数字消息从显示器传输到手持式接收器的方法
公开(公告)号：US07990292B2
公开(公告)日：2011-08-02
申请号：US12111125
申请日：2008-04-28
申请人： Dirk Marien
发明人： Dirk Marien
IPC分类号： H03M5/16 , H03M7/12
CPC分类号： G06F21/606
摘要： The invention relates to a method to efficiently transmit a digital message over a unidirectional optical link, such as the link between a computer screen and a security token equipped with photosensitive elements. It is an object of this invention to provide a source coding scheme that is optimized for transmissions of alphanumerical data containing frequent occurrences of numerals and less frequent occurrences of non-numerical data. This is achieved by using a modified Huffman code for source coding, consisting of a nibble-based prefix-free binary code. The output of the coder is efficiently mapped onto a 6B4T channel code, wherein unused ternary codewords can be used to signal data-link layer events. This efficient signalling of data-link layer events, in turn, allows for a synchronization scheme based on repeated transmissions of a finite-length message, combined with an out-of-band clock signal.
摘要翻译：本发明涉及一种通过诸如计算机屏幕和装备有感光元件的安全令牌之间的链接的单向光学链路来有效地发送数字消息的方法。本发明的一个目的是提供一种源代码编码方案，该方案针对包含频繁出现的数字的字母数字数据的传输进行优化，并且不频繁出现非数字数据。这通过使用用于源编码的修改的霍夫曼码来实现，该编码由基于半字节的前缀无二进制码组成。编码器的输出被有效地映射到6B4T信道码，其中未使用的三进制码字可以用于信号数据链路层事件。数据链路层事件的这种有效的信令反过来允许基于与带外时钟信号组合的有限长度消息的重复传输的同步方案。

48. 发明申请

US20090045988A1 Methods and Systems for Modifying the Statistical Distribution of Symbols in a Coded Message 失效
标题翻译：用于修改编码消息中符号的统计分布的方法和系统
公开(公告)号：US20090045988A1
公开(公告)日：2009-02-19
申请号：US12188261
申请日：2008-08-08
申请人： Peter Lablans
发明人： Peter Lablans
IPC分类号： H03M5/16
CPC分类号： H04L9/0662 , H04L2209/12
摘要： A method for coding a message of a plurality of m-state symbols into a coded message of n-state symbols wherein n>m is disclosed. A method to make the distribution of states of n-state symbols a uniform distribution is also disclosed. A coding rule is initiated based on a distribution of states of m-state symbols. A method of coding the coding rule by transposition is also provided. In one embodiment a coded message of n-state symbols has symbols that each have a unique state. A system for executing the coding and decoding methods is also disclosed.
摘要翻译：一种用于将多个m状态符号的消息编码成n状态符号的编码消息的方法，其中n> m被公开。还公开了使n态符号的状态分布均匀分布的方法。基于m状态符号的状态分布来启动编码规则。还提供了通过转置编码编码规则的方法。在一个实施例中，n状态符号的编码消息具有每个具有独特状态的符号。还公开了一种用于执行编码和解码方法的系统。

49. 发明授权

US6040709A Ternary signal input circuit 失效
标题翻译：三进制信号输入电路
公开(公告)号：US6040709A
公开(公告)日：2000-03-21
申请号：US82561
申请日：1998-05-21
申请人： Kazunori Kishimoto
发明人： Kazunori Kishimoto
IPC分类号： H03M5/16 , H04L25/49 , H03K19/01 , H03K19/02
CPC分类号： H03M5/16
摘要： A ternary signal input circuit includes two inverters having opposite hysteresis characteristics, respectively, a NOR gate for producing an output signal indicative of an inversion of the logical sum of output signals from the inverters, and a AND gate for producing an output signal indicative of the logical product of output signals from the inverters. The ternary signal input circuit, composed only of digital components, converts a ternary signal supplied through a transformer into binary signals and outputs the binary signals. The ternary signal input circuit has a relatively simple circuit arrangement and will take up a relatively small area on an LSI chip when it is incorporated into the LSI chip.
摘要翻译：三态信号输入电路分别包括具有相反磁滞特性的两个反相器，NOR门，用于产生指示来自反相器的输出信号的逻辑和的反相的输出信号;以及与门，用于产生指示来自逆变器的输出信号的逻辑积。由数字组件组成的三态信号输入电路将通过变压器提供的三态信号转换为二进制信号并输出二进制信号。三元信号输入电路具有相对简单的电路布置，并且当其被并入LSI芯片时将占据LSI芯片上相对较小的面积。

50. 发明授权

US5912563A Trinary signal apparatus and method 失效
标题翻译：三叉信号装置及方法
公开(公告)号：US5912563A
公开(公告)日：1999-06-15
申请号：US862132
申请日：1997-05-22
申请人： Paul Jeffrey Garnett
发明人： Paul Jeffrey Garnett
IPC分类号： H03K19/20 , H03M5/16 , H04L25/49 , H03K19/00
CPC分类号： H03M5/16 , H04L25/4923
摘要： Extended trinary signal apparatus includes window comparator logic having first and second inputs for first and second trinary input signals, wherein each the trinary input signal can be a high, low or mid state, and an output for outputting signals dependent on the states of the first and second trinary input signals. A switch, which is connected to one of the first and second inputs, can be selectively activated in one phase to set the one of the first and second inputs to a state other than the mid state and can be inactive in another phase. Control logic is responsive to output signals from the window comparator output during the one and the other phase to provide extended trinary decoding of the trinary input signals. In this manner ninth and tenth input combinations can be identified by detecting whether two inputs which show a mid state are electrically connected to each other or not, this being achieved by selectively pulling one of the inputs to a predetermined state and determining whether the other input follows or not. Trinary encoding can thus be extended to provide ten, rather than the conventional nine states from two inputs.
摘要翻译：扩展三态信号装置包括窗口比较器逻辑，其具有用于第一和第二三进制输入信号的第一和第二输入，其中每个三进制输入信号可以是高，低或中等状态，以及用于输出取决于第一和第二三态输入信号的状态的信号的输出和第二三进制输入信号。连接到第一和第二输入中的一个的开关可以在一个相位中选择性地激活，以将第一和第二输入中的一个设置为除了中间状态之外的状态，并且可以在另一个阶段中不起作用。在一个和另一个相位期间，控制逻辑响应来自窗口比较器输出的输出信号，以提供三进制输入信号的扩展三进制解码。以这种方式，可以通过检测表示中间状态的两个输入是否彼此电连接来识别第九和第十输入组合，这通过选择性地将输入中的一个拉到预定状态并确定另一个输入遵循与否因此，可以扩展三进制编码，以从两个输入提供十个而不是常规的九个状态。

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