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41. 发明专利

JPH07307665A VOLTAGE-CONTROLLED OSCILLATOR THAT OPERATES WITH DIGITAL CONTROL LOAD IN PHASE-LOCKED LOOP 失效
公开(公告)号：JPH07307665A
公开(公告)日：1995-11-21
申请号：JP31114093
申请日：1993-11-17
申请人： CODEX CORP
发明人： AAMATSUDO EICHI ATORISU , BENJIYAMIN SHII PIITAASON , RANII ERU PAAKAA
IPC分类号： H03L7/113 , H03K3/03 , H03K3/354 , H03L7/08 , H03L7/099 , H03L7/10 , H03L7/191
摘要： PURPOSE: To realize a phase locked loop operating with desired frequencies without depending on the fluctuation of temperature or a process. CONSTITUTION: This phase locked loop 10 operates without depending on the fluctuation of temperature or a process by digitally adding a load 38 to a VCO 22 until a desired operating frequency is obtained. Plural current mirrors 164-166 are controlled for increasing the switching currents of an invertor in a VCO so that the VCO can reach a high output frequency in a process in the worst case without delaying a response to a loop node voltage 18 of the VCO. A frequency range detector 34 monitors the output frequency of the VCO, transmits a control signal to a load control circuit 38, activates a digital load, and decrease the VCO to the desired operating frequency.

42. 发明专利

JPH0774629A FREQUENCY SYNTHESIZER 失效
公开(公告)号：JPH0774629A
公开(公告)日：1995-03-17
申请号：JP29709493
申请日：1993-11-26
申请人： ALCATEL STANDARD ELECTRICA
发明人： ARUFUONSO FUERUNANDESU DEYURAN , MARIANO PERESU ABADEIA , ANJIERU GONZARESU AHIJIYADO
IPC分类号： H03L7/16 , H03L7/087 , H03L7/191
摘要： PURPOSE: To obtain a frequency synthesizer provided with a phase locked loop which reduces the switching time between channels without increasing the complexity of the filter of the synthesizer nor giving any influence the stability of the synthesizer. CONSTITUTION: A frequency synthesizer is provided with a phase locked loop incorporating a reference signal generator 1, a first phase detector 2, a first low-pass filter 3, a voltage-controlled oscillator 4, and a frequency divider 5 which generates a first output signal 10 having the 1/N frequency of input signals 17 and the divider 5 supplies a second output signal 11 which is shifted in phase by 90 deg. from the first output signal 10 to a second phase detector 6 together with a reference signal 9, generates a second phase error signal 13 which has the quadrature phase of a first phase error signal 12, and supplies the signal 13 to a quadrature phase correlator 8 through a second low-pass filter 7. The correlator 8 generates an output signal 16 having an amplitude which is proportional to the frequency difference between the reference signal and the output signal of the divider 5 and supplies the signal 16 to the oscillator 4.

43. 发明专利

JPH05268079A 失效
公开(公告)号：JPH05268079A
公开(公告)日：1993-10-15
申请号：JP16795592
申请日：1992-06-25
IPC分类号： H03L7/22 , H03L7/087 , H03L7/191 , H03L7/18
摘要： PURPOSE: To provide a frequency synthesizing circuit which improves the control speed and the phase noise in a control band width in comparison with a simple phase control circuit. CONSTITUTION: A frequency synthesizer consists of plural branches 1 and 2, an oscillator 7 which supplies a reference signal to them, and a control unit 11 which controls frequency dividers 6 and 9 in respective branches. The branch 1 consists of a phase discriminator 3, a low pass filter 4, a voltage controlled oscillator 5, and a frequency divider 6 having a frequency division ratio (k). The phase discriminator 3 receives the reference signal and the output signal of the frequency divider 6. The output is inputted to the voltage controlled oscillator 5 through the low pass filter 4. The output of the oscillator 5 is inputted and supplied to frequency dividers 6 and 9. In the following branch 2, the reference signal passing a delay device 10 and the output signal supplied by the frequency divider 9 are compared with each other, and the output is inputted to the low pass filter 4. This output drives the voltage controlled oscillator 5, and the output is inputted to frequency dividers 6 and 9. A control signal 11 releases the related frequency divider 9 after the delay time of the delay element 10.

44. 发明专利

JPH05243986A 失效
公开(公告)号：JPH05243986A
公开(公告)日：1993-09-21
申请号：JP22936692
申请日：1992-08-05
申请人： FLUKE MFG CO JOHN
发明人： FUREDERITSUKU JIEI TEREUSUKII , ERITSUKU AARU DORATSUKAA
IPC分类号： H03L7/08 , H03L7/087 , H03L7/18 , H03L7/191 , H03L7/199
摘要： PURPOSE: To attenuate phase noise which a frequency dividing circuit generates and to improve the ratio of a signal against noise in a phase locked loop. CONSTITUTION: A voltage control oscillator 102 generates a variable frequency output signal in response to a composite control signal. A variable frequency divider 104 frequency-divides the frequency of a variable frequency output signal by a value which can be selected and they generate plural feedback signals fmb containing signal components and noise components. The phases of the respective signal components of the feedback signals are substantially equal and the noise components do not have correlation. A control circuit 106 generates the plural control signals in response to the phase difference of the plural feedback signals and the reference signal fr, adds the signal components of the control signals by linear overlapping, adds the noise components of the control signals by the square root of the sum of square and generates the composite control signal.

45. 发明专利

JPH0556049B2 失效
公开(公告)号：JPH0556049B2
公开(公告)日：1993-08-18
申请号：JP9206583
申请日：1983-05-25
申请人： SONY CORP
发明人： OKASHIN YAMATO
IPC分类号： H03K5/26 , H03D13/00 , H03L7/085 , H03L7/191

46. 发明专利

JPH0331016B2 失效
公开(公告)号：JPH0331016B2
公开(公告)日：1991-05-02
申请号：JP19641782
申请日：1982-11-08
申请人： SANYO ELECTRIC CO
发明人： TOKUMATSU HIROSHI
IPC分类号： H03L7/08 , H03L7/089 , H03L7/191

47. 发明专利

JPS56103540A PLL CIRCUIT 失效
公开(公告)号：JPS56103540A
公开(公告)日：1981-08-18
申请号：JP17310179
申请日：1979-12-29
申请人： CLARION CO LTD
发明人： OUSAKA HIROSHI , HONMA AKIRA , KIZAKI YOSHIO
IPC分类号： H03L7/08 , H03L7/191
摘要： PURPOSE:To prevent a malfunction caused by a mixture of noise and other factors, by using the voltage controlling oscillator in a PLL circuit for the clock source of a counting circuit in common. CONSTITUTION:The PLL circuit is composed of the phase comparator 4, LPF5, voltage controlling oscillator 2 and frequency 3. The output of the oscillator 2 is counted by the counting circuit 16 when the terminal Q of the FF12 is at an L level, and the FF12 is inverted when the circuit 16 counts up to the set number. The output of the NAND gate 14 is inhibited by the output of the FF12 during working of the counting circuit. Accordingly no malfunction is caused although the noise mixes at the input terminal 13.

48. 发明专利

JPS5291634A PHASE SUPPRESSING OSCILLATOR 失效
公开(公告)号：JPS5291634A
公开(公告)日：1977-08-02
申请号：JP597177
申请日：1977-01-24
申请人： SPERRY RAND CORP
发明人： BURUUSU JIEEMUZU ROJIYAAZU
IPC分类号： G11B20/14 , H03L7/08 , H03L7/089 , H03L7/191 , H03L7/20

49. 发明专利

JP4322319B2 Video device 失效
公开(公告)号：JP4322319B2
公开(公告)日：2009-08-26
申请号：JP7912395
申请日：1995-04-04
申请人：アールシーエートムソンライセンシングコーポレイシヨンRca Thomson Licensing Corporation
发明人：デンホランダーヴィレム
IPC分类号： H04N5/06 , H04N5/18 , G11B20/02 , H03L7/085 , H03L7/191 , H04N5/12 , H04N9/72
CPC分类号： H04N5/126 , H03L7/085 , H03L7/191

50. 发明专利

JP3617456B2 Pll circuit and optical communication receiving device 有权
公开(公告)号：JP3617456B2
公开(公告)日：2005-02-02
申请号：JP2001004616
申请日：2001-01-12
申请人：ソニー株式会社
发明人：徹竹下 , 隆志西村
IPC分类号： H03D13/00 , H03L7/08 , H03L7/087 , H03L7/089 , H03L7/191 , H04L7/033
CPC分类号： H03D13/004 , H03L7/087 , H03L7/0891 , H03L7/191 , H04L7/033

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