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41. 发明公开

EP2482463A1 Delta-sigma modulator and signal processing system 审中-公开
标题翻译： Delta-Sigma-Modulator和Signalverarbeitungssystem
公开(公告)号：EP2482463A1
公开(公告)日：2012-08-01
申请号：EP12151715.5
申请日：2012-01-19
申请人： Sony Corporation
发明人： Niwa, Atsumi , Ueno, Yosuke
IPC分类号： H03M3/00
CPC分类号： H03M3/424 , H03M3/448 , H03M3/452 , H03M3/454
摘要： A ΔΣ modulator includes: a plurality of integrators cascaded to an input of an analog signal; a quantizer for quantizing an output signal of the integrator at a last stage and outputting a resultant digital signal; a DA converter for feedback for converting the digital signal obtained by the quantizer into an analog signal and supplying the analog signal to an input side of at least the integrator at a first stage; and an adder, arranged at an input stage side of the integrator at the last stage, for adding an output of the integrator at a preceding stage of the integrator at the last stage to at least one path signal supplied from at least another path via a first resistor having at least a first coefficient. The integrator at the last stage includes an operational amplifier, an integration capacitor, and a second resistor having a second coefficient.
摘要翻译： “£调制器包括：级联到模拟信号的输入的多个积分器; 量化器，用于在最后阶段量化积分器的输出信号，并输出所得数字信号; 用于将由量化器获得的数字信号转换为模拟信号的反馈的DA转换器，并且在第一级将模拟信号提供给至少积分器的输入端; 以及加法器，布置在最后级的积分器的输入级侧，用于将最后级的积分器的前级的积分器的输出与从至少另一路径经由至少一个路径信号提供的至少一个路径信号相加第一电阻器具有至少第一系数。最后阶段的积分器包括运算放大器，积分电容器和具有第二系数的第二电阻器。

42. 发明授权

EP1980021B1 CONTINUOUS-TIME SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER WITH CAPACITOR AND/OR RESISTANCE DIGITAL SELF-CALIBRATION MEANS FOR RC SPREAD COMPENSATION 有权
标题翻译：具有自校准电容器和/或电阻钢筋混凝土SPREAD补偿时间连续Σ-Δ模数转换器
公开(公告)号：EP1980021B1
公开(公告)日：2009-12-02
申请号：EP07700660.9
申请日：2007-01-22
申请人： NXP B.V.
发明人： LE GUILLOU, Yann
IPC分类号： H03M3/00
CPC分类号： H03M3/386 , H03M3/43 , H03M3/448 , H03M3/452

43. 发明公开

EP2002553A2 TRANSCEIVER HAVING MULTIPLE SIGNAL PROCESSING MODES OF OPERATION 有权
标题翻译：多信号接收器模式
公开(公告)号：EP2002553A2
公开(公告)日：2008-12-17
申请号：EP07754386.6
申请日：2007-03-29
申请人： Silicon Laboratories Inc.
发明人： DER, Lawrence , TUTTLE, George, T. , PIOVACCARI, Alessandro , XIN, Chunyu , HABAN, Scott , ELENES, Javier , KASHA, Dan , VANCORENLAND, Peter
IPC分类号： H04B1/40
CPC分类号： H04B1/40 , H03M3/398 , H03M3/40 , H03M3/448 , H03M3/452 , H03M3/50
摘要： A transceiver includes a processor and an analog-to-digital converter. The processor is adapted to in a transmit mode of the transceiver, generate a modulated signal in response to a first digital signal. In a receive mode of the transceiver, the processor is adapted to generate a demodulated signal in response to a second digital signal. The analog-to-digital converter provides the first digital signal in the transmit mode and provides the second digital signal in the receive mode.

44. 发明公开

EP1384327A2 METHOD AND SYSTEM FOR OPERATING TWO OR MORE INTEGRATORS WITH DIFFERENT POWER SUPPLIES FOR AN ANALOG-TO-DIGITAL DELTA-SIGMA MODULATOR 有权
标题翻译：方法和系统中运行的两个或多个斜坡具有不同电源的模拟/数字Δ-Σ调制器
公开(公告)号：EP1384327A2
公开(公告)日：2004-01-28
申请号：EP02728988.3
申请日：2002-04-25
申请人： Cirrus Logic, Inc.
发明人： TUCKER, John, Christopher
IPC分类号： H03M3/00
CPC分类号： H03M3/32 , H03M3/424 , H03M3/448 , H03M3/452 , H03M3/454
摘要： A method and system are disclosed for operating two or more integrator amplifiers with different power supplies for a modulator of an analog-to-digital ('A/D') converter. A first, upstream integrator (int1) is operated with one power supply, and the other downstream integrator(s) is/are operated with at least another power supply (INT2). The modulator has amplifiers with coefficient gains having values that are determined and set so that voltage levels for the at least another integrator are maintained within operating and output limits. An integrating coefficient gain (K1) for the first integrator is set to have a sufficiently large value so that an integrating capacitor can be made small for the one integrator. Another integrating coefficient gain (K2) for a second integrator is set to have a sufficiently small value so that an output voltage from the first integrator is sufficiently attenuated to a voltage value within an operating range of the second integrator.

45. 发明公开

EP1263144A1 Delta sigma type AD converter 有权
标题翻译： Sigma-Delta模拟数字Wandler
公开(公告)号：EP1263144A1
公开(公告)日：2002-12-04
申请号：EP02253249.3
申请日：2002-05-09
申请人： Pioneer Corporation
发明人： Yamamoto, Yuji, c/o Pioneer Corporation
IPC分类号： H03M3/02
CPC分类号： H03M3/448 , H03M3/406 , H03M3/454
摘要： On a first stage of the delta sigma type AD converter (20) for quantizing an input analog signal, converting it to an output digital signal, and outputting, the computing element (102) adds a feedback signal from a second stage DA converter (114) and subtracts a feedback signal in which the output of the delay unit (103) is multiplied at a coefficient α with a coefficient buffer (104) and a feedback signal from the delay unit (105), the input analog signal is output to a computing element (107) on a post stage, and on the second stage, feedback by a coefficient β, different from a coefficient α, is executed. The frequency characteristic of quantization noise Q(Z) selects coefficients α, β so appropriately that transmission zero points are provided above and below the central frequency of an input analog signal, and the quantization noise can be damped in the range of a wide bandwidth.
摘要翻译：在ΔΣ型AD转换器（20）的第一级上，用于对输入的模拟信号进行量化，将其转换为输出数字信号，并输出，计算元件（102）将来自第二级DA转换器（114）的反馈信号），并且将延迟单元（103）的输出与系数缓冲器（104）的系数α和来自延迟单元（105）的反馈信号相乘的反馈信号相减，输出模拟信号被输出到执行后级的计算元件（107），并且在第二级上执行与系数α不同的系数β的反馈。量化噪声Q（Z）的频率特性选择系数α，β，使得在输入模拟信号的中心频率之上和之下提供传输零点，并且量化噪声可以在宽带宽的范围内被衰减。

46. 发明专利

JP5456888B2 Integrator 有权
公开(公告)号：JP5456888B2
公开(公告)日：2014-04-02
申请号：JP2012515400
申请日：2010-06-18
申请人：エスティー‐エリクソン、ソシエテ、アノニム
发明人：バス、プッター
IPC分类号： G06G7/184 , H03M3/02
CPC分类号： H03L7/24 , G06G7/18 , H03K7/06 , H03M3/43 , H03M3/448 , H03M3/452

47. 发明专利

JP2013246166A Vehicle-borne radar systems with continuous-time, sigma delta analog-to-digital converters, and methods of their operation 审中-公开
标题翻译：具有连续时间的车载雷达雷达系统，SIGMA DELTA模拟数字转换器及其操作方法
公开(公告)号：JP2013246166A
公开(公告)日：2013-12-09
申请号：JP2013103808
申请日：2013-05-16
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： BRANDT BRASWELL , DOUGLAS A GARRITY , MOHAMMAD NIZAM U KABIR
IPC分类号： G01S13/93 , B60R21/00 , G01S13/34 , G08G1/16
CPC分类号： G01S13/34 , G01S7/352 , G01S13/931 , G01S2013/9314 , G01S2013/9321 , G01S2013/9325 , G01S2013/9332 , G01S2013/9342 , G01S2013/9346 , G01S2013/9375 , G01S2013/9378 , G01S2013/9385 , H03M3/424 , H03M3/448 , H03M3/452 , H03M3/454
摘要： PROBLEM TO BE SOLVED: To provide vehicle-borne radar systems, and methods of their operation.SOLUTION: The vehicle-borne radar system includes a transmit path and a first receive path. The transmit path is capable of producing a signal for transmission over an air interface (e.g., a frequency modulated continuous wave (FMCW) signal). The receive path includes a continuous-time (CT) sigma delta analog-to-digital converter (ADC), and the receive path is capable of receiving a reflected version of the signal from the air interface, and converting the reflected version along the receive path into a sequence of digital samples using the CT sigma delta ADC. In an embodiment, the transmit path and the receive path are integrated onto a single integrated circuit.
摘要翻译：要解决的问题：提供车载雷达系统及其运行方法。解决方案：车载雷达系统包括发射路径和第一接收路径。发射路径能够产生用于通过空中接口传输的信号（例如，调频连续波（FMCW）信号）。接收路径包括连续时间（CT）Σ-Δ模数转换器（ADC），并且接收路径能够从空中接口接收信号的反射版本，并沿接收器转换反射版本使用CT西格玛Delta ADC的数字采样序列。在一个实施例中，发射路径和接收路径被集成到单个集成电路上。

48. 发明专利

JP4660444B2 Control method, and a delta-sigma modulator of the delta-sigma modulator 有权
公开(公告)号：JP4660444B2
公开(公告)日：2011-03-30
申请号：JP2006244378
申请日：2006-09-08
申请人：パナソニック株式会社
发明人：智晃前田 , 泰司秋月 , 寿史足立
IPC分类号： H03M3/02
CPC分类号： H03M3/374 , H03M3/43 , H03M3/448 , H03M3/454

49. 发明公开

EP1980021A1 CONTINUOUS-TIME SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER WITH CAPACITOR AND/OR RESISTANCE DIGITAL SELF-CALIBRATION MEANS FOR RC SPREAD COMPENSATION 有权
标题翻译：具有自校准电容器和/或电阻钢筋混凝土SPREAD补偿时间连续Σ-Δ模数转换器
公开(公告)号：EP1980021A1
公开(公告)日：2008-10-15
申请号：EP07700660.9
申请日：2007-01-22
申请人： NXP B.V.
发明人： LE GUILLOU, Yann
IPC分类号： H03M3/00
CPC分类号： H03M3/386 , H03M3/43 , H03M3/448 , H03M3/452
摘要： A continuous-time sigma-delta analog-to-digital converter (CV) comprises i) a signal path (SP) comprising at least one combiner (Cl) for combining analog signals to convert with feedback analog signals, at least two integrators (Hl, H5), mounted in series, to integrate the combined analog signals, a quantizer (Q) for converting the integrated signals into digital signals, and a decimation filter (DF) for filtering digital signals, and ii) a feedback path (FP) comprising at least a digital-to-analog converter (DAC) for converting the digital signals output by the quantizer (Q) into feedback analog signals intended for the combiner (Cl). Each integrator (Hl, H5) comprises variable capacitance means arranged to be set in chosen states define by the values of a digital word, to present chosen capacitances. The converter (CV) also comprises a self-calibration control means (CCM) arranged a) to generate a digital word with a chosen first value, b) to estimate an in-band noise IBN(n) from the filtered digital signals and to compare this IBN(n) to the preceding IBN(n-l), c) to modify the digital word value to decrease the capacitance of each integrator from a chosen decrement when IBN(n) is smaller than IBN(n-l), d) to iterate steps b) and c) till IBN(n) be greater than IBN(n-l), and to choose as calibration digital word value the value corresponding to IBN(n- 1) to set the calibration state of the variable capacitance means.

50. 发明公开

EP1668856A2 VARIABLE CODER APPARATUS FOR RESONANT POWER CONVERSION AND METHOD 有权
标题翻译：可变编码器装置共振能量转换和程序
公开(公告)号：EP1668856A2
公开(公告)日：2006-06-14
申请号：EP04786458.2
申请日：2004-08-04
申请人： STMicroelectronics, Inc
发明人： NORSWORTHY, Steven, R. , REDGRAVE, Jason, Rupert
IPC分类号： H04L25/49
CPC分类号： H03M3/392 , H03M3/394 , H03M3/424 , H03M3/448 , H03M3/454 , H03M3/498
摘要： A noise-shaping coder with variable or reconfigurable characteristics is disclosed. In one exemplary embodiment, an improved apparatus for signal modulation is disclosed. The apparatus (see figure 1) generally comprises a noise-shaping coder having programmable coefficients, (see figure 1, CSEL), programmable coder order (see figure 1, MSEL), programmable oversampling frequency (see figure 1, CKEN), and/or programmable dither (see figure 1, D). In a second exemplary embodiment, an improved method for implementing noise shaping coding is disclosed. The apparatus generally compromises a means for switching from one order coder to another order coder, as well as switching oversampling frequency.

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