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    • 41. 发明申请
      US20110006851A1 Unit inverter having linearly varying delay response characteristic and digitally controlled oscillator including the unit inverter 审中-公开
    • Unit inverter having linearly varying delay response characteristic and digitally controlled oscillator including the unit inverter
    • 具有线性变化延迟响应特性的单元逆变器和包括单元逆变器的数字控制振荡器
    • US20110006851A1
    • 2011-01-13
    • US12661934
    • 2010-03-26
    • Bong-jin Kim
    • Bong-jin Kim
    • H03K3/03
    • H03K5/133 , H03K2005/00065 , H03K2005/00221 , H03L7/0995
    • A Digitally Controlled Oscillator (DCO) including a unit inverter cell whose output frequency linearly varies according to a digital control signal, the unit inverter cell linearly varying a delay response characteristic of an output signal with respect to an input signal supplied from an input terminal, in response to a reference signal and a zeroth control signal, and including a reference cell and a first selecting cell. The reference cell transmits the output signal to an output terminal, wherein the output signal is obtained by reversing a phase of the input signal in response to the reference signal and a reverse reference signal obtained by reversing a phase of the reference signal. The number of transistors forming the reference cell and the first selecting cell and sizes of the transistors are equal.
    • 一种数字控制振荡器（DCO），包括输出频率根据数字控制信号线性地变化的单位反相器单元，单位反相器单元相对于从输入端提供的输入信号线性地改变输出信号的延迟响应特性， 响应于参考信号和第零控制信号，并且包括参考单元和第一选择单元。 参考单元将输出信号发送到输出端，其中通过响应于参考信号反转输入信号的相位和通过反转参考信号的相位获得的反向参考信号来获得输出信号。 形成参考单元和第一选择单元的晶体管的数量和晶体管的尺寸相等。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 42. 发明申请
      US20090273382A1 CIRCUIT AND METHOD FOR CORRECTING DUTY CYCLE 有权
    • CIRCUIT AND METHOD FOR CORRECTING DUTY CYCLE
    • 校正周期的电路和方法
    • US20090273382A1
    • 2009-11-05
    • US12500007
    • 2009-07-09
    • Dong Suk Shin , Hyun Woo Lee , Won Joo Yun
    • Dong Suk Shin , Hyun Woo Lee , Won Joo Yun
    • H03K3/017
    • H03K5/1565 , H03K2005/00058 , H03K2005/00221
    • A circuit configured to correct a duty cycle includes a clock dividing unit configured to delay an input clock signal by a specified delay amount and to generate a plurality of delayed clock signals, a clock selection unit configured to output any one among the plurality of delayed clock signals as a selected delayed clock signal in response to duty ratio information of the input clock signal, an edge control unit configured to generate a falling clock signal by controlling a falling edge of the selected delayed clock signal and to generate a rising clock signal by controlling a falling edge of the input clock signal based on information regarding a difference between lengths of a high duration and a low duration of the input clock signal, and a phase mixing unit for mixing phases of the falling clock signal and the rising clock signal and generating an output clock signal.
    • 配置为校正占空比的电路包括时钟分频单元，被配置为将输入时钟信号延迟指定的延迟量并产生多个延迟时钟信号;时钟选择单元，被配置为输出多个延迟时钟 信号作为响应于输入时钟信号的占空比信息的选择的延迟时钟信号;边缘控制单元，被配置为通过控制所选择的延迟时钟信号的下降沿来产生下降时钟信号，并通过控制产生上升时钟信号 基于关于输入时钟信号的高持续时间和低持续时间之间的差的信息的输入时钟信号的下降沿，以及用于混合下降时钟信号和上升时钟信号的相位的相位混合单元，并产生 输出时钟信号。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 46. 发明授权
      US07411434B2 Digitally programmable delay circuit with process point tracking 有权
    • Digitally programmable delay circuit with process point tracking
    • 具有过程点跟踪功能的数字可编程延迟电路
    • US07411434B2
    • 2008-08-12
    • US11684087
    • 2007-03-09
    • Adam L. Carley , Daniel J. Allen , James E. Mandry
    • Adam L. Carley , Daniel J. Allen , James E. Mandry
    • H03L7/06
    • H03K5/133 , H03K2005/00065 , H03K2005/00221
    • A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed. One or more of the transistors are selected by a delay control signal to impose a delay amount to the edge, wherein the delay control signal is based on a desired delay amount and a measure of instantaneous process, voltage and temperature conditions of an integrated circuit in which the plurality of transistors are implemented. A selector circuit is responsive to the delay control signal and converts the delay control signal into one or more transistor selection signals to activate one or more of the plurality of transistors. The plurality of transistors may comprise a first sub-circuit having a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other in a ladder configuration, and a second sub-circuit comprising a plurality of transistors of a second type (e.g., N-type) connected in parallel with each other and in a ladder configuration. The overall delay imposed on the edge after it has passed through both sub-circuits has delay contributions from both types of transistors. The delay circuit may have enhanced performance because of finer delay control granularity by providing a first circuit stage that comprises a plurality of transistors for relatively fine delay adjustment to the edge and a second circuit stage that comprises a plurality of transistors for relatively coarse delay adjustment to the edge. A combination of one or more of the transistors in the first and second circuit stages may be selected to produce numerous steps or increments of delay adjustability.
    • 一种数字可编程延迟电路，包括彼此并联连接的多个晶体管以及承载具有待延迟边缘的信号的线。 通过延迟控制信号选择一个或多个晶体管，以对边缘施加延迟量，其中延迟控制信号基于期望的延迟量和集成电路的瞬时过程，电压和温度条件的测量 多个晶体管被实现。 选择器电路响应延迟控制信号并将延迟控制信号转换成一个或多个晶体管选择信号以激活多个晶体管中的一个或多个。 多个晶体管可以包括具有第一类型的多个晶体管（例如，P型）的第一子电路，其以梯形配置彼此并联连接，第二子电路包括多个晶体管， 第二类型（例如，N型），彼此并联并且以梯形结构连接。 在通过两个子电路之后施加在边缘上的总体延迟具有来自两种类型的晶体管的延迟贡献。 延迟电路可以通过提供包括多个用于对边缘进行相对精细的延迟调整的多个晶体管的第一电路级，由于更精细的延迟控制粒度而具有增强的性能，第二电路级包括用于相对粗略延迟调整的多个晶体管 边缘。 可以选择第一和第二电路级中的一个或多个晶体管的组合以产生许多延迟可调性的步骤或增量。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 47. 发明授权
      US06664837B1 Delay line trim unit having consistent performance under varying process and temperature conditions 有权
    • Delay line trim unit having consistent performance under varying process and temperature conditions
    • 延迟线修剪单元在不同的工艺和温度条件下具有一致的性能
    • US06664837B1
    • 2003-12-16
    • US10247241
    • 2002-09-18
    • Kwansuhk Oh , Raymond C. Pang
    • Kwansuhk Oh , Raymond C. Pang
    • H03H1126
    • H03L7/0814 , H03K5/133 , H03K2005/00065 , H03K2005/00221 , H03L7/0818
    • A delay circuit has a delay that is consistent under varying process and temperature conditions. The delay through a delay path is controlled by inserting resistors on the pull-up and pull-down paths of the delaying inverters. Each resistor has a resistance value that is determined by a varying a number of enabled similarly-sized transistors coupled in parallel across the resistor, rather than by varying the size of a single transistor. In one embodiment, a first transistor in each resistor is always enabled, while additional transistors are enabled using select signals. In one embodiment, the select signals are provided by configuration memory cells in a PLD. Other embodiments include additional delay paths and a multiplexer circuit that selects one of the delay paths. The described delay circuit is particularly useful in a DLL trim unit, where variations between resistors can cause jitter and locking problems in the DLL.
    • 延迟电路具有在变化的工艺和温度条件下是一致的延迟。 通过延迟路径的延迟通过在延迟逆变器的上拉和下拉路径上插入电阻来控制。 每个电阻器具有由在电阻器上并联耦合的使能相似尺寸的晶体管的数量的变化确定的电阻值，而不是通过改变单个晶体管的尺寸来确定。 在一个实施例中，每个电阻器中的第一晶体管总是使能，而使用选择信号启用附加晶体管。 在一个实施例中，选择信号由PLD中的配置存储器单元提供。 其他实施例包括额外的延迟路径和选择延迟路径之一的多路复用器电路。 所描述的延迟电路在DLL修剪单元中特别有用，其中电阻之间的变化可能导致DLL中的抖动和锁定问题。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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