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41. 发明公开

EP1001334A3 Logarithm / antilog calculator 有权
标题翻译：对数/反对数计算器
公开(公告)号：EP1001334A3
公开(公告)日：2002-11-27
申请号：EP99203820.8
申请日：1999-11-16
申请人： Texas Instruments Incorporated
发明人： Allred, Rustin W.
IPC分类号： G06F7/556
CPC分类号： G06F7/556
摘要： A digital signal system (100) for determining an approximate logarithm of a value of x having a base b . The approximate logarithm includes an integer portion ( i ) and a decimal portion ( f ). The system comprises an input (12) for receiving a signal, and circuitry (18) for measuring an attribute of the signal. The attribute relates at least in part the value of x . The system further comprises circuitry (104) for identifying a bounded region within which x falls. The bounded region is one of a plurality of bounded regions, where each of the plurality of bounded regions corresponds to a different value of an integer n and is bounded on a lower side by b n and on a higher side by b n +1 . Additionally, the identified bounded region identifies the integer portion of the approximate logarithm. The system further comprises circuitry (106, 108) for determining the decimal portion of the approximate logarithm by mapping a portion of x to a point along a curve representing an approximation of a portion of an actual logarithm value of x .
摘要翻译：一种数字信号系统（100），用于确定具有基数b的x值的近似对数。近似对数包括整数部分（i）和小数部分（f）。该系统包括用于接收信号的输入端（12）和用于测量信号的属性的电路（18）。该属性至少部分涉及x的值。该系统还包括用于识别x落入其中的有界区域的电路（104）。有界区域是多个有界区域中的一个，其中多个有界区域中的每一个对应于整数n的不同值并且在较低侧通过bn和在较高侧通过bn + 1界定。另外，识别的有界区域标识近似对数的整数部分。该系统还包括用于通过将x的一部分映射到表示x的实际对数值的一部分的近似的曲线上的点来确定近似对数的小数部分的电路（106,108）。

42. 发明公开

EP1032892A2 METHODS APPARATUS AND COMPUTER PROGRAM PRODUCTS FOR ACCUMULATING LOGARITHMIC VALUES 有权
标题翻译：方法，设备和计算机程序产品积累BY对数值
公开(公告)号：EP1032892A2
公开(公告)日：2000-09-06
申请号：EP98948477.9
申请日：1998-09-23
申请人： ERICSSON INC.
发明人： DENT, Paul, Wilkinson
IPC分类号： G06F17/10
CPC分类号： G06F7/556 , G06F7/49
摘要： The sum of a plurality of logarithmic numbers is determined by expressing the logarithmic numbers as one of a predetermined values. For example, the numbers may be analog values which may be sampled by an 8-bit AtoD converter to be expressed as one of a possible 256 values. The number of occurrences for each of the values is accumulated in bins (counters) and the sum is determined by a summation of the logarithmic numbers based on processing of the counts rather than the logarithmic numbers themselves. Bin counts are reduced iteratively by replacing counts greater than 1 by incrementing the count of a proportionately higher value bin until only counts of 1 or zero remain. These counts are then combined to provide only a single counter with a non-zero count value which indicates the accumulated signal strength of the signal strength measurements. The invention may further be provided using single bit memory elements and byte processing with look-up tables. In a further aspect of the present invention enhanced precision signed logarithmic magnitude expressions of numbers are combined utilizing Zech logarithmic values applied iteratively to a most significant and least significant component of the difference in the logmagnitude of the numbers to be combined.

43. 发明公开

EP0807287A4 LOGARITHM/INVERSE-LOGARITHM CONVERTER UTILIZING A TRUNCATED TAYLOR SERIES AND METHOD OF USE THEREOF 失效
标题翻译：对数/对数INVERTED变换器USING A CUT泰勒级数及其使用方法FOR该转换器
公开(公告)号：EP0807287A4
公开(公告)日：1999-09-01
申请号：EP96902095
申请日：1996-01-03
申请人： MOTOROLA INC
发明人： DWORKIN JAMES DOUGLAS , BUSS JOHN MICHAEL
IPC分类号： G06F1/03 , G06F7/556 , H03M7/50 , G06F7/00 , G06F7/38 , G06F15/00 , G06G7/24 , G06G7/26
CPC分类号： G06F7/556 , G06F1/0307 , H03M7/50
摘要： A converter which may be used for implementing either logarithmic or inverse-logarithmic functions is disclosed. The converter includes a memory (22), two multipliers (28 and 30), and two adders (32 and 34). The memory (22) stores a plurality of coefficients which are based on a second-order Taylor polynomial used to estimate a logarithmic or inverse-logarithmic function over a domain of input values. A method of using the converter is also disclosed.

44. 发明公开

EP0849664A2 Apparatus for computing transcendental functions quickly 失效
标题翻译： Gerätzur schneller Berechnung von tranzedentale Funktionen
公开(公告)号：EP0849664A2
公开(公告)日：1998-06-24
申请号：EP97310118.1
申请日：1997-12-15
申请人： Metaflow Technologies, Inc.
发明人： Rarick, Leonard D.
IPC分类号： G06F7/548 , G06F7/556
CPC分类号： G06F7/556 , G06F7/548
摘要： The invention provides a method and system for computing transcendental functions quickly: (1) the multiply ALU is enhanced to add a term to the product, (2) rounding operations for intermediate multiplies are skipped, and (3) the Taylor series is separated into two partial series which are performed in parallel. Transcendental functions with ten terms (e.g., SIN or COS), are thus performed in about ten clock times.
摘要翻译：本发明提供了一种用于快速计算超越函数的方法和系统：（1）增加乘法ALU以向产品添加项，（2）跳过中间乘数的舍入运算，（3）泰勒级数分为并行执行两个部分系列。因此，在十个时钟内执行具有十个术语（例如，SIN或COS）的超验功能。

45. 发明申请

WO2019085379A1 深度学习softmax分类器的硬件实现电路及其控制方法审中-公开
公开(公告)号：WO2019085379A1
公开(公告)日：2019-05-09
申请号：PCT/CN2018/080608
申请日：2018-03-27
申请人：北京深鉴智能科技有限公司
发明人：张玉 , 康君龙 , 谢东亮
IPC分类号： G06N3/00
CPC分类号： G06F7/485 , G06F7/487 , G06F7/556 , G06N3/00 , G06N3/08
摘要：本公开提供一种深度学习softmax分类器的硬件实现电路及其控制方法。硬件实现电路(100)包括：接口数据读控制模块(110)，用于从外部存储器中读取计算数据给指数计算模块(120)；指数计算模块(120)，用于并行地进行浮点元素的指数运算；加法树模块(130)，用于进行指数计算模块(120)的运算结果的累加运算；缓存模块(140)，用于缓存指数计算模块(120)的运算结果以及加法树模块(130)的累加运算结果；除法计算模块(150)，用于并行地计算各个浮点元素的指数运算结果与所有浮点元素指数运算结果之和的比值；接口数据写控制模块(160)，用于将除法计算模块(150)的计算结果写入外部存储器。

46. 发明申请

WO2016037885A1 SYSTEM AND METHOD FOR ONE-TIME CHINESE-REMAINDER-THEOREM EXPONENTIATION FOR CRYPTOGRAPHIC ALGORYTHMS 审中-公开
标题翻译：系统和方法用于一次性中立理论的理论指导
公开(公告)号：WO2016037885A1
公开(公告)日：2016-03-17
申请号：PCT/EP2015/069867
申请日：2015-08-31
申请人： GEMALTO SA
发明人： VIGILANT, David
IPC分类号： G06F7/72
CPC分类号： H04L9/004 , G06F7/556 , G06F7/723 , G06F2207/7261 , H04L9/003 , H04L9/302
摘要： A system, method and computer-readable storage medium with instructions for protecting an electronic device against fault attack. The technology includes operating the electronic device to determine two half-size exponents, dp and dq , from the exponent d ; to split the base m into two sub- bases mp and mq determined from the base m ; and to iteratively compute a decryption result S by repeatedly multiplying an accumulator A by m , mp , mq or 1 depending on the values of the i -th bit of dp and dq for each iteration /'. Other systems and methods are disclosed.
摘要翻译：一种具有用于保护电子设备免受故障攻击的指令的系统，方法和计算机可读存储介质。该技术包括操作电子设备以从指数d确定两个半角指数dp和dq; 将碱m分解成从碱m确定的两个亚碱基mp和mq; 并且通过根据每次迭代的'dp和dq的第i位的值重复地将累加器A乘以m，mp，mq或1来迭代地计算解密结果S. 公开了其它系统和方法。

47. 发明申请

WO2014200501A1 COMPILER OPTIMIZATION FOR COMPLEX EXPONENTIAL CALCULATIONS 审中-公开
标题翻译：复合计算的编译器优化
公开(公告)号：WO2014200501A1
公开(公告)日：2014-12-18
申请号：PCT/US2013/045782
申请日：2013-06-14
申请人： INTEL CORPORATION , BIKSHANDI, Ganesh , KIM, Daehyun
发明人： BIKSHANDI, Ganesh , KIM, Daehyun
IPC分类号： G06F17/10 , G06F9/45
CPC分类号： G06F8/443 , G06F7/4806 , G06F7/556 , G06F8/4434 , G06F8/452 , G06F17/10 , G06F2207/5561
摘要： Technologies for optimizing complex exponential calculations include a computing device with optimizing compiler. The compiler parses source code, optimizes the parsed representation of the source code, and generates output code. During optimization, the compiler identifies a loop in the source code including a call to the exponential function having an argument that is a loop-invariant complex number multiplied by the loop index variable. The compiler tiles the loop to generate a pair of nested loops. The compiler generates code to pre-compute the exponential function and store the resulting values in a pair of coefficient arrays. The size of each coefficient array may be equal to the square root of the number of loop iterations. The compiler applies rewrite rules to replace the exponential function call with a multiplicative expression of one element from each of the coefficient arrays. Other embodiments are described and claimed.
摘要翻译：用于优化复数指数计算的技术包括具有优化编译器的计算设备。编译器解析源代码，优化源代码的解析表示，并生成输出代码。在优化期间，编译器识别源代码中的循环，包括对具有循环不变复数乘以循环索引变量的参数的指数函数的调用。编译器平铺循环以生成一对嵌套循环。编译器生成代码以预先计算指数函数，并将结果值存储在一对系数数组中。每个系数数组的大小可以等于循环次数的平方根。编译器使用重写规则来替换来自每个系数数组的一个元素的乘法表达式的指数函数调用。描述和要求保护其他实施例。

48. 发明申请

WO2005119427A2 PIPELINED REAL OR COMPLEX ALU 审中-公开
标题翻译：管道实或复合ALU
公开(公告)号：WO2005119427A2
公开(公告)日：2005-12-15
申请号：PCT/EP2005/005911
申请日：2005-06-02
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (publ) , DENT, Paul, Wilkinson
发明人： DENT, Paul, Wilkinson
IPC分类号： G06F7/483
CPC分类号： G06F7/556 , G06F7/4806
摘要： A method and ALU for implementing logarithmic arithmetic in a multi-stage pipeline is described herein. According to one embodiment, a master function is decomposed into two or more sub-functions. Memory associated with the pipeline stores a look-up table for each stage of the pipeline, where each table represents function values generated based on the corresponding sub-function, and where the look-up table associated with one stage differs from the look-up table(s) associated with at least one other stage. Each stage computes a stage output based on the stage input and the corresponding look-up table. By combining the stage outputs, the multi-stage pipeline outputs the logarithmic arithmetic output.
摘要翻译：这里描述了用于在多级流水线中实现对数运算的方法和ALU。根据一个实施例，主功能被分解成两个或更多个子功能。与流水线相关联的存储器存储管道的每个级的查找表，其中每个表表示基于相应的子功能生成的功能值，并且与一个级相关联的查找表与查找不同与至少一个其他阶段相关联的表。每个阶段基于舞台输入和相应的查找表来计算舞台输出。通过组合级输出，多级流水线输出对数运算输出。

49. 发明申请

WO2002077797A1 PRODUCING A LOGARITHMIC SIGNAL APPROXIMATION WITH VAIRABLE PRECISION 审中-公开
标题翻译：生产具有可靠精度的逻辑信号近似
公开(公告)号：WO2002077797A1
公开(公告)日：2002-10-03
申请号：PCT/US2002/006629
申请日：2002-03-05
申请人： MOTOROLA, INC.
发明人： CHATTERJEE, Manjirnath
IPC分类号： G06F7/556
CPC分类号： G06F7/556 , G06F7/74
摘要： A system and method for producing an output logarithmic digital signal from an input digital signal having a plurality of bit values in which the output logarithmic signal has a precision defined by a parameter is described. The system (45) includes a search circuit (50), an interpolation circuit (55) in coupled with the search circuit, a shift circuit (60) in coupled with the interpolation circuit and a combiner (65) that produces an output logarithmic digital signal (90) from a received search circuit output (75) and a received shift circuit output (88).
摘要翻译：描述了一种用于从具有多个位值的输入数字信号产生输出对数数字信号的系统和方法，其中输出对数信号具有由参数定义的精度。系统（45）包括搜索电路（50），与搜索电路耦合的内插电路（55），与内插电路耦合的移位电路（60）和产生输出对数数字来自接收到的搜索电路输出（75）的信号（90）和接收到的移位电路输出（88）。

50. 发明申请

WO1997005543A1 LOG CONVERTER UTILIZING OFFSET AND METHOD OF USE THEREOF 审中-公开
标题翻译：日志转换器利用偏移及其使用方法
公开(公告)号：WO1997005543A1
公开(公告)日：1997-02-13
申请号：PCT/US1996006692
申请日：1996-05-10
申请人： MOTOROLA INC. , PAN, ShaoWei , WANG, Shay-Ping, Thomas
发明人： MOTOROLA INC.
IPC分类号： G06F07/00
CPC分类号： H03M7/50 , G06F1/035 , G06F7/556
摘要： A digital log converter is provided which includes a comparator (10) and a log signal generator (20). Upon receiving a digital input signal (12), the comparator (10) determines whether an upper bit-slice of the input signal (12) equals zero. If the upper bit-slice is zero, the log signal generator (20) subtracts an offset from at least one parameter to generate a log signal (16); otherwise, the log signal generator (20) interpolates the at least one parameter and a lower bit-slice of the input signal (12) to generate the log signal (16).
摘要翻译：提供了一种数字对数转换器，其包括比较器（10）和对数信号发生器（20）。在接收到数字输入信号（12）时，比较器（10）确定输入信号（12）的高位位元是否等于零。如果上位片为零，则对数信号发生器（20）从至少一个参数减去偏移量以产生对数信号（16）; 否则，对数信号发生器（20）插入输入信号（12）的至少一个参数和较低位片，以产生对数信号（16）。

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