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    • 44. 发明授权
    • Semiconductor memory system with programmable address decoder
    • 具有可编程地址解码器的半导体存储器系统
    • US4893281A
    • 1990-01-09
    • US911926
    • 1986-09-25
    • Masashi Hashimoto
    • Masashi Hashimoto
    • G11C17/00G11C8/10G11C16/06
    • G11C8/10
    • A semiconductor memory system using address signals each consisting of a first predetermined number of logic bits, comprising a memory array having a number of memory cells and access lines along which the memory cells are arranged in rows or columns, and a programmable address decoder responsive to a second number of logic bits of each of the address signals, the second predetermined number being not larger than the first predetermined number. The address decoder comprises a plurality of address generation networks commonly connected to the address bus and respectively associated with the access lines and is operative to generate a predetermined sequence of address bits representing a desired address for one of the access lines in the memory array in response to the second predetermined number of address bits of each of the address signals. Each of the address generation networks comprises a plurality of programmable memory cells and a switching circuit for selecting memory cells out of all the programmable memory cells of each of the address generation networks in response to the predetermined sequence of the address bits generated in the address decoder.
    • 一种半导体存储器系统,其使用每个由第一预定数量的逻辑位组成的地址信号,所述地址信号包括存储器阵列,所述存储器阵列具有多个存储单元和存储器单元以行或列排列的存取线,以及响应于 每个地址信号的第二数量的逻辑位,第二预定数不大于第一预定数。 地址解码器包括通常连接到地址总线并且分别与接入线相关联的多个地址生成网络,并且可操作地响应地产生表示存储器阵列中的一个接入线的期望地址的预定顺序的地址位 到每个地址信号的第二预定数量的地址位。 每个地址生成网络包括多个可编程存储器单元和切换电路,用于响应于在地址解码器中产生的地址位的预定顺序,从每个地址生成网络的所有可编程存储器单元中选择存储单元 。
    • 46. 发明授权
    • FIFO memory including dynamic memory elements
    • FIFO存储器包括动态存储器元件
    • US4882710A
    • 1989-11-21
    • US94943
    • 1987-09-09
    • Masashi HashimotoSasaki KenjiMasayoshi Nomura
    • Masashi HashimotoSasaki KenjiMasayoshi Nomura
    • G11C11/401G06F5/10G11C7/00
    • G06F5/10G11C7/00
    • A FIFO memory is provided with individual arrays of dynamic memory cells and includes a dedicated write line buffer memory and a dedicated read line buffer memory operably connected thereto. First and second line buffer memories are also provided in conjunction with the write line buffer memory and the read line buffer memory so as to permit a faster response to the input and output of data with respect to the FIFO memory. Data may be alternately written into either one of the line buffer memories as a lead-in to the subsequent writing of data in the dynamic memory arrays via the write line buffer memory. Data read out from the other line buffer memory may occur simultaneously. The FIFO memory may serve as a video data frame memory for storing a frame of a video screen image. Where video data is continuously written into the FIFO memory, either the preceding video data frame or the current video data frame that is being written is subject to read out depending on the timing of a read reset signal relative to the last write reset signal. The write line buffer memory and the read line buffer memory are operable independently of each other, and may have simultaneous cycle times without any synchronization therebetween. The first and second line buffer memories preferably comprise static type memory elements to facilitate rapid data read out therefrom in response to a read reset signal.
    • FIFO存储器具有单独的动态存储器单元阵列,并且包括可操作地连接到其上的专用写行缓冲存储器和专用读行缓冲存储器。 第一和第二行缓冲存储器还与写行缓冲存储器和读行缓冲存储器一起提供,以便允许对FIFO存储器的数据的输入和输出的更快的响应。 可以将数据交替地写入行缓冲存储器中的任何一个作为通过写行缓冲存储器在动态存储器阵列中随后写入数据的导入。 从其他行缓冲存储器读出的数据可能同时发生。 FIFO存储器可以用作存储视频屏幕图像的帧的视频数据帧存储器。 在视频数据被连续地写入FIFO存储器的情况下,根据读取复位信号相对于最后写入复位信号的定时,前面的视频数据帧或正被​​写入的当前视频数据帧被读出。 写行缓冲存储器和读行缓冲存储器可彼此独立地操作,并且可以具有同时的周期时间,而在它们之间没有任何同步。 第一行缓冲存储器和第二行缓冲存储器优选地包括静态型存储器元件,以便响应读取的复位信号便于从其读出数据。
    • 47. 发明授权
    • Semiconductor ROM with reduced supply voltage requirement
    • 半导体ROM具有降低的电源电压要求
    • US4862413A
    • 1989-08-29
    • US180648
    • 1988-04-04
    • Masashi HashimotoTadashi Tachibana
    • Masashi HashimotoTadashi Tachibana
    • G11C17/18G11C5/14G11C17/12
    • G11C5/147G11C17/12
    • A memory device including a voltage stepdown circuit is proposed in which a reduced reference voltage is produced from a supplied reference voltage and is passed to the selected one of the row lines of the memory array after all the row lines are discharged to ground potential, while the supplied reference voltage is fed directly, viz., without reduction, to all the control circuits of the device. The voltage stepdown circuit provided in the memory device is thus relieved from the burden to supply current to the control circuits and has only to feed the selected one of the row lines so that the field-effect transistors forming the voltage stepdown circuit can be fabricated to have channel regions with significantly reduced widths.
    • 提出了包括降压电路的存储器件,其中从所提供的参考电压产生降低的参考电压,并且在所有行线被放电到地电位之后被传递到存储器阵列的选定行之一行,同时 所提供的参考电压直接馈送到设备的所有控制电路,即不减少。 因此,设置在存储装置中的降压电路免除了向控制电路提供电流的负担,并且仅供给所选择的一行行线,使得形成降压电路的场效应晶体管可以制造成 具有显着减小宽度的通道区域。
    • 50. 发明授权
    • Semicarbazide derivatives, processes for preparation thereof and
pharmaceutical composition comprising the same
    • 氨基脲衍生物,其制备方法和包含其的药物组合物
    • US4725608A
    • 1988-02-16
    • US673845
    • 1984-11-21
    • Osamu NakaguchiNorihiko ShimazakiYoshio KawaiMasashi HashimotoMichie Nakatuka
    • Osamu NakaguchiNorihiko ShimazakiYoshio KawaiMasashi HashimotoMichie Nakatuka
    • C07D203/26C07D211/70C07D213/89C07D237/04C07D295/28A61K31/435C07D211/98
    • C07D213/89C07D203/26C07D211/70C07D237/04C07D295/32
    • New semicarbazide derivatives of the formula: ##STR1## wherein R.sup.1 is hydrogen,R.sup.2 is hydrogen, lower alkyl, ar(lower)alkyl, lower alkenyl or aryl,R.sup.3 is lower alkyl, ar(lower)alkyl, lower alkenyl or aryl, orR.sup.2 and R.sup.3 are taken together to form (C.sub.2 -C.sub.6)alkylidene group optionally substituted with aryl or taken together with the adjacent nitrogen atom to form a saturated or unsaturated, 5- or 6-membered heterocyclic group optionally substituted with aryl; orR.sup.1 and R.sup.2 are taken together with the adjacent nitrogen atoms to form a saturated or unsaturated, 5- or 6-membered heterocyclic group or 1,2-diazaspiroalkane-1,2-diyl group,R.sup.3 is hydrogen, lower alkyl, ar(lower)alkyl, lower alkenyl or aryl;R.sup.4 is aryl which may have substituent(s) selected from lower alkyl, halogen, lower alkoxy, lower alkylamino, halo(lower)alkyl, hydroxy, lower alkanoyl, esterified carboxy and carboxy,R.sup.5 is hydrogen or lower alkyl, andX is O or S, provided that the lower alkyl group for R.sup.3 is (C.sub.3 -C.sub.6)alkyl, when R.sup.2 is hydrogen or (C.sub.1 -C.sub.2) alkyl and R.sup.4 is aryl optionally having substituent(s) selected from groups consisting of halogen, lower alkyl, lower alkoxy and halo(lower)alkyl, and pharmaceutically acceptable salts thereof, and processes for preparation thereof and pharmaceutical composition comprising the same.These derivatives and salts thereof are useful as antiinflammatory and analgesic agents.
    • 新的下式的氨基脲衍生物:其中R1是氢,R2是氢,低级烷基,芳基(低级)烷基,低级烯基或芳基,R3是低级烷基,芳基(低级)烷基,低级烯基或芳基,或 R2和R3一起形成任选被芳基取代的(C 2 -C 6)亚烷基或与相邻的氮原子一起形成任选被芳基取代的饱和或不饱和的5或6元杂环基; 或者R1和R2与相邻的氮原子一起形成饱和或不饱和的5或6元杂环基或1,2-二氮杂环烷-1,2-二基,R3是氢,低级烷基,ar( 低级)烷基,低级烯基或芳基; R4是可以具有选自低级烷基,卤素,低级烷氧基,低级烷基氨基,卤代(低级)烷基,羟基,低级烷酰基,酯化羧基和羧基的取代基的芳基,R 5是氢或低级烷基,X是O 或者当R 2为氢或(C 1 -C 2)烷基,且R 4为任选具有选自以下的取代基的芳基时,R 3的低级烷基为(C 3 -C 6)烷基:(C 3 -C 6)烷基,低级烷基, 低级烷氧基和卤代(低级)烷基及其药学上可接受的盐,及其制备方法和包含其的药物组合物。 这些衍生物和其盐可用作抗炎和止痛剂。