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    • 42. 发明授权
    • Device for controlling access from a plurality of masters to shared memory composed of a plurality of banks each having a plurality of pages
    • 用于控制从多个主机到由多个存储体组成的共享存储器的访问的装置,每个存储体具有多个页面
    • US08095744B2
    • 2012-01-10
    • US12267014
    • 2008-11-07
    • Isao KawamotoYoshiharu Watanabe
    • Isao KawamotoYoshiharu Watanabe
    • G06F13/18G06F3/00G06F12/00G06F13/36G06F13/00
    • G06F13/1663Y02D10/14
    • The memory access device includes: a plurality of command division sections provided for a plurality of masters; a plurality of inter-master arbitration sections provided for a plurality of banks; and a memory control section. Each of the command division sections divides a command issued by the corresponding master into a plurality of micro-commands when the access region of the command is over two or more banks among the plurality of banks, each of the micro-commands being a command accessing only one of the two or more banks, and gives each of the micro-commands to an inter-master arbitration section corresponding to the bank including the access region of the micro-command. Each of the inter-master arbitration sections arbitrates micro-commands given from the command division sections to select one. The memory control section selects one of a plurality of micro-commands selected by the inter-master arbitration sections to perform memory access.
    • 存储器访问装置包括:为多个主器件提供的多个命令分割部分; 为多个银行提供的多个主控间仲裁部分; 和存储器控制部分。 当命令的访问区域在多个存储体中的两个或更多个存储体上时,每个命令分割部分将由相应主机发出的命令分成多个微命令,每个微命令是命令访问 仅将两个或更多个存储体中的一个存储,并且将每个微指令分配给与包括微指令的存取区域的存储体对应的主站间仲裁部分。 每个主控间仲裁部分仲裁从命令分割部分给出的微指令以选择一个。 存储器控制部分选择由主机间仲裁部分选择的多个微指令之一来执行存储器访问。
    • 43. 发明授权
    • Software processing method and software processing system
    • 软件处理方法和软件处理系统
    • US07584464B2
    • 2009-09-01
    • US10727055
    • 2003-12-04
    • Kei YonedaIsao KawamotoSeiji KitaTakaaki Matsubayashi
    • Kei YonedaIsao KawamotoSeiji KitaTakaaki Matsubayashi
    • G06F9/44G06F9/45
    • G06F9/52G06F2209/508
    • In a multi-processor system constituted by a processor such as a CPU and a DSP, in which the processor and the DSP have an external memory and a bus as shared resources and the DSP carries out a process in response to a processing request from the processor, a monitoring step for status of use includes a step of monitoring the status of use of the DSP, and when contention information obtained in the monitoring step for the status of use indicates frequent uses, an altering step for software process appropriately alters a software processing method to be executed, and switches the corresponding process to an equivalent process so that it becomes possible to avoid bus contention, and consequently to prevent a reduction in the processing speed.
    • 在由诸如CPU和DSP的处理器构成的多处理器系统中,其中处理器和DSP具有外部存储器和总线作为共享资源,并且DSP响应于来自所述处理器的处理请求执行处理 处理器,用于使用状态的监视步骤包括监视DSP的使用状态的步骤,并且当在用于使用状态的监视步骤中获得的争用信息指示频繁使用时,软件处理的改变步骤适当地改变软件 处理方法,并将相应的处理切换到等效处理,使得可以避免总线争用,从而防止处理速度的降低。