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41. 发明申请

US20050237816A1 Operation scheme for spectrum shift in charge trapping non-volatile memory 有权
标题翻译：电荷捕获非易失性存储器频谱移位操作方案
公开(公告)号：US20050237816A1
公开(公告)日：2005-10-27
申请号：US10876378
申请日：2004-06-24
申请人： Hang-Ting Lue , Yen-Hao Shih , Kuang Yeu Hsieh , Ming-Hsiu Lee , Chao-I Wu , Tzu-Hsuan Hsu
发明人： Hang-Ting Lue , Yen-Hao Shih , Kuang Yeu Hsieh , Ming-Hsiu Lee , Chao-I Wu , Tzu-Hsuan Hsu
IPC分类号： G11C11/36 , G11C16/04 , G11C16/34
CPC分类号： G11C16/3481 , G11C16/0466 , G11C16/3436
摘要： A memory cell with a charge trapping structure is programmed using refill cycles that include a program pulse followed by a charge balancing pulse that causes ejection of electrons from the charge trapping structure. The refill cycle causes a blue spectrum shift in the charge trap distribution in the charge trapping structure. The algorithm includes program verify operations after the program pulse, and completes when a successful program verify operation occurs after a number of refill cycles.
摘要翻译：具有电荷俘获结构的存储单元使用包括编程脉冲，随后是电荷平衡脉冲的再填充循环被编程，该电荷平衡脉冲引起电荷从电荷捕获结构的喷出。充电周期引起电荷捕获结构中电荷陷阱分布的蓝色光谱偏移。该算法包括在程序脉冲之后的程序验证操作，并且在多个填充循环之后发生成功的程序验证操作时完成。

42. 发明授权

US08482052B2 Silicon on insulator and thin film transistor bandgap engineered split gate memory 有权
标题翻译：硅绝缘体和薄膜晶体管带隙设计的分离栅极存储器
公开(公告)号：US08482052B2
公开(公告)日：2013-07-09
申请号：US12056489
申请日：2008-03-27
申请人： Hang-Ting Lue , Erh-Kun Lai
发明人： Hang-Ting Lue , Erh-Kun Lai
IPC分类号： H01L29/792 , H01L29/788
CPC分类号： H01L29/66833 , G11C16/0466 , G11C16/0483 , G11C16/0491 , H01L21/28282 , H01L27/115 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/792
摘要： Thin film transistor memory cells are stackable, and employ bandgap engineered tunneling layers in a junction free, NAND configuration, that can be arranged in 3D arrays. The memory cells have a channel region in a semiconductor strip formed on an insulating layer, a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure having a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region, a charge storage layer disposed above the tunnel dielectric structure, an insulating layer disposed above the charge storage layer, and a gate electrode disposed above the insulating layer.
摘要翻译：薄膜晶体管存储单元是可堆叠的，并且采用无结构的NAND配置的带隙工程隧道层，其可以排列成3D阵列。所述存储单元具有在绝缘层上形成的半导体条中的沟道区，设置在所述沟道区上方的隧道电介质结构，所述隧道电介质结构具有多层结构，所述多层结构包括至少一层具有低于空穴穿透势垒高度的层。在与沟道区域的界面处，设置在隧道介电结构上方的电荷存储层，设置在电荷存储层上方的绝缘层和设置在绝缘层上方的栅电极。

43. 发明申请

US20120220111A1 INJECTION METHOD WITH SCHOTTKY SOURCE/DRAIN 审中-公开
标题翻译：注射方法与肖特源/排水
公开(公告)号：US20120220111A1
公开(公告)日：2012-08-30
申请号：US13463264
申请日：2012-05-03
申请人： Yi-Hsuan Hsiao , Erh-Kun Lai , Hang-Ting Lue
发明人： Yi-Hsuan Hsiao , Erh-Kun Lai , Hang-Ting Lue
IPC分类号： H01L21/04
CPC分类号： H01L29/665 , G11C16/0408 , H01L29/40117 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes.
摘要翻译：描述了具有肖特基源和漏极的非易失性存储单元的注入方法。载流子注入效率由硅化物和硅的界面特性控制。通过控制栅极和源极/漏极的重叠以及通过控制注入，激活和/或栅极过程来修改肖特基势垒。

44. 发明申请

US20080002477A1 METHOD FOR MANUFACTURING MEMORY CELL 有权
标题翻译：制造记忆细胞的方法
公开(公告)号：US20080002477A1
公开(公告)日：2008-01-03
申请号：US11836142
申请日：2007-08-09
申请人： Tzu-Hsuan Hsu , Erh-Kun Lai , Hang-Ting Lue , Chia-Hua Ho
发明人： Tzu-Hsuan Hsu , Erh-Kun Lai , Hang-Ting Lue , Chia-Hua Ho
IPC分类号： G11C11/34 , H01L21/36
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/42352
摘要： The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory comprises a straddle gate, a carrier trapping layer and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping layer is located between the straddle gate and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.
摘要翻译：本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构底物。存储器包括跨骑门，载体俘获层和至少两个源极/漏极区域。跨门位于基板上，跨越垂直翅片结构。载体捕获层位于跨门和基板之间。源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

45. 发明授权

US08183617B2 Injection method with Schottky source/drain 有权
标题翻译：肖特基源/漏极注入法
公开(公告)号：US08183617B2
公开(公告)日：2012-05-22
申请号：US12430817
申请日：2009-04-27
申请人： Yi-Hsuan Hsiao , Erh-Kun Lai , Hang-Ting Lue
发明人： Yi-Hsuan Hsiao , Erh-Kun Lai , Hang-Ting Lue
IPC分类号： H01L29/76
CPC分类号： H01L29/665 , G11C16/0408 , H01L21/28282 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes.
摘要翻译：描述了具有肖特基源和漏极的非易失性存储单元的注入方法。载流子注入效率由硅化物和硅的界面特性控制。通过控制栅极和源极/漏极的重叠以及通过控制注入，激活和/或栅极过程来修改肖特基势垒。

46. 发明授权

US07468299B2 Non-volatile memory cells and methods of manufacturing the same 有权
标题翻译：非易失性存储单元及其制造方法
公开(公告)号：US07468299B2
公开(公告)日：2008-12-23
申请号：US11197659
申请日：2005-08-04
申请人： ChiaHua Ho , Erh-Kun Lai , Hang-Ting Lue
发明人： ChiaHua Ho , Erh-Kun Lai , Hang-Ting Lue
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： Methods for forming non-volatile memory cells include: (a) providing a semiconductor substrate having at least two source/drain regions, and a dielectric material disposed on the substrate above at least one of the at least two source/drain regions wherein the dielectric material has an exposed surface, and wherein the at least two source/drain regions are separated by a recess trench having an exposed surface, wherein the trench extends downward into the substrate to a depth position below the at least two source/drain regions; (b) forming a charge-trapping layer on the exposed surfaces of the dielectric material and the recess trench; and (c) forming a gate above the charge-trapping layer.
摘要翻译：用于形成非易失性存储单元的方法包括：（a）提供具有至少两个源极/漏极区域的半导体衬底和设置在至少两个源极/漏极区域中的至少一个的衬底上的电介质材料，其中电介质材料具有暴露的表面，并且其中所述至少两个源极/漏极区域被具有暴露表面的凹槽分隔开，其中所述沟槽向下延伸到所述衬底中至所述至少两个源极/漏极区域下方的深度位置; （b）在电介质材料和凹槽沟的暴露表面上形成电荷捕获层; 和（c）在电荷俘获层上形成栅极。

47. 发明申请

US20070258291A1 Methods and apparatus for implementing bit-by-bit erase of a flash memory device 有权
标题翻译：用于实现闪存设备的逐位擦除的方法和设备
公开(公告)号：US20070258291A1
公开(公告)日：2007-11-08
申请号：US11549502
申请日：2006-10-13
申请人： Hang-Ting Lue , Erh Kun Lai
发明人： Hang-Ting Lue , Erh Kun Lai
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/0483 , G11C16/0466 , G11C16/12 , G11C16/14 , G11C16/3418 , G11C16/3427 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11568 , H01L27/1203
摘要： A NAND memory device is constructed using Silicon On Insulator (SOI) techniques. In particular, Thin Film Transistor (TFT) techniques can be used to fabricate the NAND Flash memory device. In both SOI and TFT structures, the body, or well, is isolated. This can be used to enable a bit-by-bit programming and erasing of individual cells and allows tight control of the threshold voltage, which can enable MLC operation.
摘要翻译： NAND存储器件使用绝缘体（SOI）技术构建。特别地，薄膜晶体管（TFT）技术可用于制造NAND闪存器件。在SOI和TFT结构中，主体或阱被隔离。这可以用于启用单个单元的逐位编程和擦除，并允许严格控制阈值电压，这可以实现MLC操作。

48. 发明授权

US08643078B2 Semiconductor structure and manufacturing method of the same 有权
标题翻译：半导体结构及其制造方法相同
公开(公告)号：US08643078B2
公开(公告)日：2014-02-04
申请号：US13443417
申请日：2012-04-10
申请人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh
发明人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh
IPC分类号： H01L29/788
CPC分类号： H01L23/3192 , H01L27/11565 , H01L27/11578 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a base, a stacked structure and a doped layer. The stacked structure is formed on the base, wherein the stacked structure comprises a plurality of conductive strips and a plurality of insulating strips, one of the conductive strips is located between adjacent two insulating strips, the stacked structure has a first side wall, and a long edge of the first side wall is extended along a channel direction. The doped layer is formed in the first side wall, wherein the doped layer is formed by an ion implantation applied to the first side wall, and an acute angle is contained between an implantation direction of the ion implantation and the first side wall.
摘要翻译：提供了一种半导体结构及其制造方法。半导体结构包括基极，层叠结构和掺杂层。堆叠结构形成在基底上，其中堆叠结构包括多个导电条和多个绝缘条，其中一个导电条位于相邻的两个绝缘条之间，该堆叠结构具有第一侧壁和第一侧壁的长边缘沿着通道方向延伸。掺杂层形成在第一侧壁中，其中通过施加到第一侧壁上的离子注入形成掺杂层，并且在离子注入的注入方向和第一侧壁之间包含锐角。

49. 发明授权

US08153491B2 Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer 有权
标题翻译：具有氧化物 - 氧化物 - 氧化物（ONO）顶部介电层的非易失性存储器半导体器件
公开(公告)号：US08153491B2
公开(公告)日：2012-04-10
申请号：US12506993
申请日：2009-07-21
申请人： Hang-Ting Lue , Erh-Kun Lai
发明人： Hang-Ting Lue , Erh-Kun Lai
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L29/513
摘要： A non-volatile memory (NVM) cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate, a drain region in a portion of the silicon substrate, and a well region disposed in a portion of the silicon substrate between the source and drain regions. The cell includes a bottom oxide layer formed on the main surface of the substrate. The bottom oxide layer is disposed on a portion of the main surface proximate the well region. The cell includes a charge storage layer disposed above the bottom oxide layer, a dielectric tunneling layer disposed above the charge storage layer and a control gate formed above the dielectric tunneling layer. The dielectric tunneling layer includes a first oxide layer, a nitride layer and a second oxide layer. Erasing the NVM cell includes applying a positive gate voltage to inject holes from the gate.
摘要翻译：非易失性存储器（NVM）单元包括具有主表面的硅衬底，硅衬底的一部分中的源极区域，硅衬底的一部分中的漏极区域和设置在硅衬底的一部分中的阱区域硅衬底在源区和漏区之间。电池包括形成在基板的主表面上的底部氧化物层。底部氧化物层设置在靠近阱区域的主表面的一部分上。电池包括设置在底部氧化物层上方的电荷存储层，设置在电荷存储层上方的电介质隧道层和形成在电介质隧道层上方的控制栅极。电介质隧道层包括第一氧化物层，氮化物层和第二氧化物层。擦除NVM单元包括施加正栅极电压以从栅极注入孔。

50. 发明授权

US07907450B2 Methods and apparatus for implementing bit-by-bit erase of a flash memory device 有权
标题翻译：用于实现闪存设备的逐位擦除的方法和设备
公开(公告)号：US07907450B2
公开(公告)日：2011-03-15
申请号：US11549502
申请日：2006-10-13
申请人： Hang-Ting Lue , Erh Kun Lai
发明人： Hang-Ting Lue , Erh Kun Lai
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/0466 , G11C16/12 , G11C16/14 , G11C16/3418 , G11C16/3427 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11568 , H01L27/1203
摘要： A NAND memory device is constructed using Silicon On Insulator (SOI) techniques. In particular, Thin Film Transistor (TFT) techniques can be used to fabricate the NAND Flash memory device. In both SOI and TFT structures, the body, or well, is isolated. This can be used to enable a bit-by-bit programming and erasing of individual cells and allows tight control of the threshold voltage, which can enable MLC operation.
摘要翻译： NAND存储器件使用绝缘体（SOI）技术构建。特别地，薄膜晶体管（TFT）技术可用于制造NAND闪存器件。在SOI和TFT结构中，主体或阱被隔离。这可以用于启用单个单元的逐位编程和擦除，并允许严格控制阈值电压，这可以实现MLC操作。

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