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    • 42. 发明授权
    • Method for identifying vehicles in electronic images
    • 电子图像识别车辆的方法
    • US07676087B2
    • 2010-03-09
    • US11523986
    • 2006-09-20
    • Arnab S. DhuaYan ZhangStephen J. Kiselewich
    • Arnab S. DhuaYan ZhangStephen J. Kiselewich
    • G06K9/00
    • G06K9/3241B60W30/08G06K9/00805G06K2209/23G06T7/70G08G1/16G08G1/166
    • A method for identifying objects in an electronic image is provided. The method includes the steps of providing an electronic source image and processing the electronic source image to identify edge pixels. The method further includes the steps of providing an electronic representation of the edge pixels and processing the electronic representation of the edge pixels to identify valid edge center pixels. The method still further includes the step of proving an electronic representation of the valid edge center pixels. Each valid edge center pixel represents the approximate center of a horizontal edge segment of a target width. The horizontal edge segment is made up of essentially contiguous edge pixels. The method also includes the steps of determining symmetry values of test regions associated with valid edge center pixels, and classifying the test regions based on factors including symmetry.
    • 提供了一种用于识别电子图像中的对象的方法。 该方法包括提供电子源图像和处理电子源图像以识别边缘像素的步骤。 该方法还包括提供边缘像素的电子表示并处理边缘像素的电子表示以识别有效边缘中心像素的步骤。 该方法还包括证明有效边缘中心像素的电子表示的步骤。 每个有效的边缘中心像素表示目标宽度的水平边缘片段的大致中心。 水平边缘段由基本上相邻的边缘像素组成。 该方法还包括以下步骤:确定与有效边缘中心像素相关联的测试区域的对称值,以及基于包括对称性的因素对测试区域进行分类。
    • 50. 发明申请
    • Glitch-free clock signal multiplexer circuit and method of operation
    • 无毛刺时钟信号多路复用电路及其操作方法
    • US20070290725A1
    • 2007-12-20
    • US11453733
    • 2006-06-14
    • Martin Saint-LaurentYan Zhang
    • Martin Saint-LaurentYan Zhang
    • G06F1/08
    • H04L7/0083G06F1/08
    • Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Reduced glitch occurs in switching from a first clock input to a second clock input driving a clock multiplexer. The clock multiplexer receives a first clock input and provides a clock output and determines a low phase output level in the clock output in response to a low phase input level in the first clock output. For a limited period of time, a low phase output level is forced irrespective of the phase level of the first clock input signal. The clock multiplexer receives a second clock input and determines a low phase input level in the second clock input signal. Switching to providing the clock output in response to the second clock input occurs during the low phase input level in the second clock input signal. Then, the output of the clock multiplexer follows the phase level of the second clock signal.
    • 用于设计和使用数字信号处理器的技术,包括(但不限于)用于处理通信(例如,CDMA)系统中的传输。 在从第一时钟输入切换到驱动时钟多路复用器的第二时钟输入时发生减小的毛刺。 时钟多路复用器接收第一时钟输入并提供时钟输出,并响应于第一时钟输出中的低相位输入电平确定时钟输出中的低相位输出电平。 在有限的时间段内,不管第一时钟输入信号的相位电平如何,都会强制执行低相输出电平。 时钟复用器接收第二时钟输入并确定第二时钟输入信号中的低相位输入电平。 响应于第二时钟输入而提供时钟输出的切换发生在第二时钟输入信号中的低相位输入电平期间。 然后,时钟复用器的输出跟随第二时钟信号的相位电平。