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41. 发明授权

US08386747B2 Processor and method for dynamic and selective alteration of address translation 有权
标题翻译：用于动态和选择性地改变地址转换的处理器和方法
公开(公告)号：US08386747B2
公开(公告)日：2013-02-26
申请号：US12483051
申请日：2009-06-11
申请人： William C. Moyer , James B. Eifert
发明人： William C. Moyer , James B. Eifert
IPC分类号： G06F13/00 , G06F13/28 , G06F9/46 , G06F9/00 , G11C8/00
CPC分类号： G06F12/1036 , G06F12/0284 , G06F12/109
摘要： Non-intrusive techniques have been developed to dynamically and selectively alter address translations performed by, or for, a processor. For example, in some embodiments, a memory management unit is configured to map from effective addresses in respective effective (or virtual) address spaces to physical addresses in the memory, wherein the mappings performed by the memory management unit are based on address translation entries of an address translation table. For a subset of less than all processes, entry selection logic selects from amongst plural alternative mappings coded in respective ones of the address translation entries. For at least some effective addresses mapped for a particular process of the subset, selection of a particular address translation entry is based on an externally sourced value. In some embodiments, only a subset of effective addresses mapped for the particular process are subject to dynamic runtime alteration of the address translation entry selection.
摘要翻译：已经开发了非侵入性技术来动态地和选择性地改变由处理器执行的或为处理器执行的地址转换。例如，在一些实施例中，存储器管理单元被配置为将相应的有效（或虚拟）地址空间中的有效地址映射到存储器中的物理地址，其中由存储器管理单元执行的映射基于地址转换条目地址转换表。对于少于所有进程的子集，条目选择逻辑从在各个地址转换条目中编码的多个备选映射中进行选择。对于为子集的特定过程映射的至少一些有效地址，特定地址转换条目的选择基于外部来源的值。在一些实施例中，仅为特定进程映射的有效地址的子集经受地址转换条目选择的动态运行时间更改。

42. 发明授权

US08364896B2 Method and apparatus for configuring a unified cache based on an associated error rate 有权
标题翻译：基于相关错误率配置统一缓存的方法和装置
公开(公告)号：US08364896B2
公开(公告)日：2013-01-29
申请号：US12234618
申请日：2008-09-20
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F12/00
CPC分类号： G06F12/0848 , G06F11/1064 , G06F12/0864 , G06F2212/1016 , G06F2212/1032 , G06F2212/601
摘要： A method of configuring a unified cache includes identifying unified cache way assignment combinations for an application unit. Each combination has an associated error rate. A combination is selected based at least in part on the associated error rate. The unified cache is configured in accordance with the selected combination for execution of the application-unit.
摘要翻译：配置统一缓存的方法包括识别应用单元的统一缓存方式分配组合。每个组合都有相关的错误率。至少部分地基于相关联的错误率来选择组合。根据用于执行应用单元的所选择的组合来配置统一高速缓存。

43. 发明授权

US08356239B2 Selective cache way mirroring 有权
标题翻译：选择性缓存方式镜像
公开(公告)号：US08356239B2
公开(公告)日：2013-01-15
申请号：US12204989
申请日：2008-09-05
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F11/00
CPC分类号： G06F12/0864 , G06F11/1064 , G06F12/126
摘要： A data processing system has cache circuitry having a plurality of ways. Mirroring control logic indicates a mirrored way pair and a non-mirrored way of the plurality of ways. The mirrored way pair has first and second ways wherein the second way is configured to store cache data fields redundant to cache data fields of the first way. In one form, comparison logic, in response to an address hitting in the first way or the second way within the mirrored way pair, performs a bit comparison between cache data from the first way addressed by an index portion of the address with cache data from the second way addressed by the index portion of the address to provide a bit parity error signal. In another form, allocation logic uses a portion of the address and line locking information to determine whether a mirrored or non-mirrored way is selected for allocation.
摘要翻译：数据处理系统具有多个方式的高速缓存电路。镜像控制逻辑指示多个方式的镜像方式对和非镜像方式。镜像方式对具有第一和第二种方式，其中第二种方式被配置为存储冗余的高速缓存数据字段以缓存第一种方式的数据字段。在一种形式中，响应于以第一种方式触发的地址或镜像方式对内的第二种方式的比较逻辑，从由地址的索引部分寻址的第一种方式的高速缓存数据与来自由地址的索引部分寻址的第二种方式来提供位奇偶校验错误信号。在另一种形式中，分配逻辑使用地址和行锁定信息的一部分来确定是否选择镜像或非镜像方式进行分配。

44. 发明申请

US20120311379A1 CONTROL OF INTERRUPT GENERATION FOR CACHE 有权
标题翻译：缓存中断生成控制
公开(公告)号：US20120311379A1
公开(公告)日：2012-12-06
申请号：US13149217
申请日：2011-05-31
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F11/16
CPC分类号： G06F12/084 , G06F11/073 , G06F11/0772 , G06F11/0793 , G06F12/0802 , G06F12/126 , G09G2360/121
摘要： A data processing device includes a cache having a plurality of cache lines. Each cache line has a lockout state that indicates whether an error has been detected for data accessed at the cache line. The lockout state of a cache line is indicated by a set of one or more lockout bits associate with the cache line. When a cache line is in a locked-out state, the cache line is not used by the cache. Accordingly, a locked-out cache line is not employed by the cache to satisfy a cache accesses, and is not used to store data retrieved from memory in response to a cache miss. In response to determining the detected error likely did not result from a hardware failure or other persistent condition, memory error management software can reset the lockout state of the cache line.
摘要翻译：数据处理装置包括具有多个高速缓存线的高速缓存。每个高速缓存行都有一个锁定状态，指示是否检测到在高速缓存行中访问的数据的错误。高速缓存行的锁定状态由与高速缓存行相关联的一个或多个锁定位的集合指示。当高速缓存行处于锁定状态时，高速缓存行不被缓存使用。因此，高速缓存不使用锁定高速缓存行来满足高速缓存访问，并且不用于存储响应于高速缓存未命中从存储器检索的数据。响应于确定检测到的错误可能不是由于硬件故障或其他持续条件而引起的，所以存储器错误管理软件可以重置高速缓存行的锁定状态。

45. 发明授权

US08291305B2 Error detection schemes for a cache in a data processing system 有权
标题翻译：数据处理系统中缓存的错误检测方案
公开(公告)号：US08291305B2
公开(公告)日：2012-10-16
申请号：US12205222
申请日：2008-09-05
申请人： William C. Moyer , Quyen Pho , Michael J. Rochford
发明人： William C. Moyer , Quyen Pho , Michael J. Rochford
IPC分类号： H03M13/00
CPC分类号： G06F11/1064 , H03M13/09 , H03M13/13
摘要： A method includes providing a cache; and providing a plurality of cache lines within the cache, wherein a first one of the plurality of cache lines has a tag entry and a data entry, wherein the tag entry has a parity field for storing one or more parity bits associated with a first portion of the tag entry, wherein the tag entry has an EDC field for storing one or more EDC check bits associated with a second portion of the tag entry and wherein the EDC check bits are used for detecting multiple bit errors, and wherein both the first parity field and the EDC field are stored in the tag entry of said first one of the plurality of cache lines.
摘要翻译：一种方法包括提供高速缓存; 并且在所述高速缓存中提供多个高速缓存线，其中所述多条高速缓存行中的第一条具有标签条目和数据条目，其中所述标签条目具有用于存储与第一部分相关联的一个或多个奇偶校验位的奇偶校验字段所述标签条目具有用于存储与所述标签条目的第二部分相关联的一个或多个EDC校验位的EDC字段，并且其中所述EDC校验位用于检测多个位错误，并且其中所述第一奇偶校验位字段和EDC字段存储在多个高速缓存线中的所述第一个高速缓存行的标签条目中。

46. 发明授权

US08255748B2 Soft error and transient error detection device and methods therefor 有权
标题翻译：软错误和瞬态误差检测装置及其方法
公开(公告)号：US08255748B2
公开(公告)日：2012-08-28
申请号：US12415338
申请日：2009-03-31
申请人： William C. Moyer , Troy L. Cooper
发明人： William C. Moyer , Troy L. Cooper
IPC分类号： G01R31/3177 , G01R31/40
CPC分类号： H03H11/26 , G01R31/31816 , H03K3/0375 , H03K3/356156 , H03K19/0075
摘要： A clock signal is received at a clock node of a latch module, and a data signal is received at a data node of the latch module. The data signal including information to be latched at a first latch of the latch module and at a second latch of the latch module. A first representation of the data signal to a first data node of the first latch is delayed relative to a second representation of the data signal to a corresponding first data node of the second latch to obtain a first timing requirement between the data signal and the clock signal relative to the first latch that is substantially different than a second timing requirement. An error signal is generated in response to different data being latched at the first latch than at the second latch.
摘要翻译：在锁存模块的时钟节点处接收时钟信号，并且在锁存模块的数据节点处接收数据信号。数据信号包括要在锁存模块的第一锁存器处锁存的信息和锁存模块的第二锁存器处的信息。数据信号对第一锁存器的第一数据节点的第一表示相对于数据信号的第二表示被延迟到第二锁存器的对应的第一数据节点，以获得数据信号和时钟之间的第一定时要求相对于第一锁存器的信号基本上不同于第二定时要求。响应于在第一锁存器处锁存的不同数据而不是在第二锁存器处产生错误信号。

47. 发明申请

US20120204012A1 CONFIGURABLE PIPELINE BASED ON ERROR DETECTION MODE IN A DATA PROCESSING SYSTEM 有权
标题翻译：基于数据处理系统中的错误检测模式的可配置管道
公开(公告)号：US20120204012A1
公开(公告)日：2012-08-09
申请号：US13446930
申请日：2012-04-13
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/30 , G06F9/302 , G06F9/305 , G06F9/312
CPC分类号： G06F9/3875 , G06F9/3004 , G06F9/30181 , G06F9/30189 , G06F9/38 , G06F9/3861 , G06F9/3867 , G06F11/1004 , G06F11/1008 , G06F11/1076
摘要： A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.
摘要翻译：一种方法包括提供具有指令流水线的数据处理器，其中指令流水线具有多个指令流水线级，并且其中多条指令流水线级包括第一指令流水线级和第二指令流水线级。该方法还包括提供数据处理器指令，使数据处理器在数据处理器指令的执行期间执行第一组计算操作，如果数据处理器指令正在执行，则在第一指令流水线阶段执行第一组计算操作执行并且已经选择了第一模式，并且如果正在执行数据处理器指令并且已经选择了第二模式，则在第二指令流水线级中执行第一组计算操作。

48. 发明申请

US20120198177A1 SELECTIVE MEMORY ACCESS TO DIFFERENT LOCAL MEMORY PORTS AND METHOD THEREOF 有权
标题翻译：选择性存储器访问不同的本地存储器端口及其方法
公开(公告)号：US20120198177A1
公开(公告)日：2012-08-02
申请号：US13016371
申请日：2011-01-28
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/1441 , G06F9/30043 , G06F9/34 , G06F9/3824 , G06F9/3842 , Y02D10/13
摘要： A data processor is disclosed that definitively determines an effective address being calculated and decoded will be associated with an address range that includes a memory local to a data processor unit, and will disable a cache access based upon a comparison between a portion of a base address and a corresponding portion of an effective address input operand. Access to the local memory can be accomplished through a first port of the local memory when it is definitively determined that the effective address will be associated with an address range. Access to the local memory cannot be accomplished through the first port of the local memory when it is not definitively determined that the effective address will be associated with the address range.
摘要翻译：公开了一种数据处理器，其确定地确定正在计算的有效地址，并将解码的地址与包括本地到数据处理器单元的存储器的地址范围相关联，并且将基于基地址的一部分之间的比较来禁用高速缓存访问以及有效地址输入操作数的对应部分。当确定有效地址将与地址范围相关联时，可以通过本地存储器的第一端口来实现对本地存储器的访问。当没有明确确定有效地址与地址范围相关联时，无法通过本地存储器的第一个端口访问本地存储器。

49. 发明授权

US08200908B2 Method for debugger initiated coherency transactions using a shared coherency manager 有权
标题翻译：使用共享一致性管理器的调试器启动的一致性事务的方法
公开(公告)号：US08200908B2
公开(公告)日：2012-06-12
申请号：US12366994
申请日：2009-02-06
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/1027
摘要： A data processing system includes a system interconnect, a first interconnect master coupled to the system interconnect, a second interconnect master coupled to the system interconnect, and a cache coherency manager coupled to the first and second interconnect masters. The first interconnect master includes a cache. The cache coherency manager provides debug cache coherency operations and non-debug cache coherency operations to the first interconnect master. The cache coherency manager generates the debug cache coherency operations in response to debug cache coherency commands from a debugger and generates the non-debug cache coherency operations in response to transactions performed by the second interconnect master on the system interconnect.
摘要翻译：数据处理系统包括系统互连，耦合到系统互连的第一互连主机，耦合到系统互连的第二互连主机，以及耦合到第一和第二互连主机的高速缓存一致性管理器。第一个互连主机包括缓存。高速缓存一致性管理器向第一互连主机提供调试高速缓存一致性操作和非调试高速缓存一致性操作。高速缓存一致性管理器响应于来自调试器的调试高速缓存一致性命令而生成调试高速缓存一致性操作，并且响应于系统互连上由第二互连主控执行的事务而生成非调试高速缓存一致性操作。

50. 发明授权

US08180969B2 Cache using pseudo least recently used (PLRU) cache replacement with locking 有权
标题翻译：使用伪最近最少使用（PLRU）高速缓存替换与缓存
公开(公告)号：US08180969B2
公开(公告)日：2012-05-15
申请号：US12014594
申请日：2008-01-15
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/122 , G06F12/126
摘要： A cache stores information in each of a plurality of cache lines. Addressing circuitry receives memory addresses for comparison with multiple ways of stored addresses to determine a hit condition representing a match of a stored address and a received address. A pseudo least recently used (PLRU) tree circuit stores one or more states of a PLRU tree and implements a tree having a plurality of levels beginning with a root and indicates one of a plurality of ways in the cache. Each level has one or more nodes. Multiple nodes within a same level are child nodes to a parent node of an immediately higher level. PLRU update circuitry that is coupled to the addressing circuitry and the PLRU tree circuit receives lock information to lock one or more lines of the cache and prevent a PLRU tree state from selecting a locked line.
摘要翻译：高速缓存将信息存储在多条高速缓存行中的每一条中。寻址电路接收用于与存储地址的多种方式进行比较的存储器地址，以确定表示存储的地址和接收到的地址的匹配的命中条件。伪最近最少使用（PLRU）树电路存储PLRU树的一个或多个状态，并实现具有从根开始的多个级别的树，并指示高速缓存中的多种方式之一。每个级别都有一个或多个节点。同一级别内的多个节点是直接更高级别的父节点的子节点。耦合到寻址电路和PLRU树电路的PLRU更新电路接收锁定信息以锁定高速缓存的一行或多行，并防止PLRU树状态选择锁定线。

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