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41. 发明授权

US06576551B1 Chemical mechanical polish planarizing method with pressure compensating layer 有权
标题翻译：化学机械抛光平面法与压力补偿层
公开(公告)号：US06576551B1
公开(公告)日：2003-06-10
申请号：US09467115
申请日：1999-12-20
申请人： Weng Chang , Chung-Shi Liu
发明人： Weng Chang , Chung-Shi Liu
IPC分类号： H01L21261
CPC分类号： H01L21/3212
摘要： A chemical mechanical polish (CMP) planarizing method for forming a chemical mechanical polish (CMP) planarized layer within a microelectronic fabrication. There is first provided a substrate. There is then formed over the substrate a chemical mechanical polish (CMP) substrate layer having an aperture formed therein. There is then formed upon the chemical mechanical polish (CMP) substrate layer and completely filling the aperture within the chemical mechanical polish (CMP) substrate layer a blanket chemical mechanical polish (CMP) planarizable layer. There is then chemical mechanical polish (CMP) planarized, while employing a chemical mechanical polish (CMP) planarizing method, the blanket chemical mechanical polish (CMP) planarizable layer to form within the aperture from the blanket chemical mechanical polish (CMP) planarizable layer a patterned chemical mechanical polish (CMP) planarized layer. Within the method, the chemical mechanical polish (CMP) substrate layer has formed therein a pressure compensating layer which compensates for a chemical mechanical polish (CMP) pressure employed within the chemical mechanical polish (CMP) planarizing method such that the patterned chemical mechanical polish (CMP) planarized layer is formed with enhanced planarity.
摘要翻译：用于在微电子制造中形成化学机械抛光（CMP）平坦化层的化学机械抛光（CMP）平面化方法。首先提供基板。然后在衬底上形成具有形成在其中的孔的化学机械抛光（CMP）衬底层。然后在化学机械抛光（CMP）衬底层上形成并且完全填充化学机械抛光（CMP）衬底层内的孔，其具有毯式化学机械抛光（CMP）可平面化层。然后，化学机械抛光（CMP）平面化，同时采用化学机械抛光（CMP）平面化方法，在毯式化学机械抛光（CMP）可平面化层a的孔内形成毯式化学机械抛光（CMP）可平面化层图案化学机械抛光（CMP）平面化层。在该方法中，化学机械抛光（CMP）衬底层中形成有压力补偿层，其补偿化学机械抛光（CMP）平面化方法中所采用的化学机械抛光（CMP）压力，使得图案化化学机械抛光 CMP）平坦化层形成具有增强的平面性。

42. 发明申请

US20060049036A1 Method and apparatus for real-time control and monitor of deposition processes 审中-公开
标题翻译：用于实时控制和监测沉积过程的方法和装置
公开(公告)号：US20060049036A1
公开(公告)日：2006-03-09
申请号：US10936905
申请日：2004-09-09
申请人： Cheng-Hung Chang , Jhi-Cherng Lu , Joung-Wei Liou , Chu-Yun Fu , Weng Chang , Syung-Ming Jang
发明人： Cheng-Hung Chang , Jhi-Cherng Lu , Joung-Wei Liou , Chu-Yun Fu , Weng Chang , Syung-Ming Jang
IPC分类号： C23C14/00
CPC分类号： C23C14/34 , C23C14/54
摘要： A method comprises measuring an RF voltage and ion current at a wafer during a plasma-enhanced deposition process, determining a sputter rate in response to the RF voltage and ion current measurements, detecting an abnormal condition in response to one of the RF voltage and ion current measurements, and sputter rate, and taking a corrective action in response to detecting an abnormal condition.
摘要翻译：一种方法包括在等离子体增强沉积过程期间测量晶片处的RF电压和离子电流，响应于RF电压和离子电流测量确定溅射速率，响应于RF电压和离子之一检测异常状况电流测量和溅射速率，并且响应于检测到异常状况采取校正动作。

43. 发明申请

US20050079801A1 Methods for enhancing within-wafer CMP uniformity 失效
公开(公告)号：US20050079801A1
公开(公告)日：2005-04-14
申请号：US10684288
申请日：2003-10-08
申请人： Weng Chang
发明人： Weng Chang
IPC分类号： B24B37/04 , B24B57/02 , B24B1/00
CPC分类号： B24B37/04 , B24B57/02
摘要： A method for enhancing uniformity in the polishing profile of a substrate during chemical mechanical polishing. According to a first embodiment, the method is adapted for a rotary-type chemical mechanical polisher and includes dispensing the polishing slurry onto the rotating polishing pad of the CMP apparatus in a polishing area on the polishing pad that contacts the entire surface area of the substrate. This facilitates substantially equal polishing rates and a substantially uniform polishing profile from the center to the edge regions on the surface of the substrate. According to a second embodiment, the method of the present invention is adapted for a linear-type chemical mechanical polisher and includes increasing the number of nozzles that dispense the slurry onto the polishing pad across the diameter or width of the substrate.

44. 发明授权

US06372632B1 Method to eliminate dishing of copper interconnects by the use of a sacrificial oxide layer 有权
标题翻译：通过使用牺牲氧化物层来消除铜互连的凹陷的方法
公开(公告)号：US06372632B1
公开(公告)日：2002-04-16
申请号：US09490138
申请日：2000-01-24
申请人： Chen-Hua Yu , Weng Chang , Jih-Chung Twu , Tsu Shih
发明人： Chen-Hua Yu , Weng Chang , Jih-Chung Twu , Tsu Shih
IPC分类号： H01L214763
CPC分类号： H01L21/7688 , H01L21/31053 , H01L21/3212 , H01L21/7684
摘要： A method of forming a planarized metal interconnect comprising the following steps. A semiconductor structure is provided. A low K dielectric layer is formed over the semiconductor structure. A sacrificial layer over is formed over the low K dielectric layer. The sacrificial layer and low K dielectric layer are patterned to form a trench within the sacrificial layer and low K dielectric layer. A barrier layer is formed over the sacrificial layer, lining the trench side walls and bottom. Metal is deposited on the barrier layer to form a metal layer filling the lined trench and blanket filling the sacrificial layer covered low K dielectric layer. The metal layer and the barrier layer are planarized, exposing the upper surface of the sacrificial layer. The sacrificial layer is removed to form a planarized metal interconnect.
摘要翻译：一种形成平面化金属互连的方法，包括以下步骤。提供半导体结构。在半导体结构上形成低K电介质层。在低K电介质层上形成牺牲层。将牺牲层和低K电介质层图案化以在牺牲层和低K电介质层内形成沟槽。在牺牲层上形成阻挡层，衬在沟槽侧壁和底部。金属沉积在阻挡层上以形成填充衬里沟槽的金属层，并覆盖填充覆盖低K电介质层的牺牲层。金属层和阻挡层被平坦化，暴露牺牲层的上表面。去除牺牲层以形成平坦化的金属互连。

45. 发明授权

US6159842A Method for fabricating a hybrid low-dielectric-constant intermetal dielectric (IMD) layer with improved reliability for multilevel interconnections 有权
标题翻译：用于制造具有改进的多电平互连可靠性的混合低介电常数金属间电介质（IMD）层的方法
公开(公告)号：US6159842A
公开(公告)日：2000-12-12
申请号：US229382
申请日：1999-01-11
申请人： Weng Chang , Yao-Yi Cheng
发明人： Weng Chang , Yao-Yi Cheng
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/00 , H01L21/70 , H01L21/77
CPC分类号： H01L21/7682 , H01L21/76801 , H01L21/76826 , H01L21/76834 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a hybrid low dielectric constant intermetal dielectric layer with improved reliability for multilevel electrical interconnections on integrated circuits is achieved. After forming metal lines for interconnecting the semiconductor devices, a protective insulating layer composed of a low-k fluorine-doped oxide (k=3.5) is deposited. A porous low-k spin-on dielectric layer (k less than 3) is formed in the gaps between the metal lines to further minimize the intralevel capacitance. A more dense low-k dielectric layer, such as FSG, is deposited on the porous layer to provide improved structural mechanical strength and over the metal lines to provide reduced intralevel capacitance. Via holes are etched in the FSG and are filled with metal plugs and the method can be repeated for additional metal levels to complete the multilevel interconnections on the integrated circuit.
摘要翻译：实现了在集成电路上制造用于多电平电互连的可靠性提高的混合低介电常数金属间介质层的方法。在形成用于互连半导体器件的金属线之后，沉积由低k氟掺杂氧化物（k = 3.5）组成的保护绝缘层。在金属线之间的间隙中形成多孔低k自旋电介质层（k小于3），以进一步最小化电容。在多孔层上沉积更致密的低k介电层，例如FSG，以提供改进的结构机械强度和金属线以提供降低的体积电容。通孔在FSG中蚀刻并填充有金属插头，并且可以重复该方法以获得额外的金属层以完成集成电路上的多层互连。

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