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41. 发明授权

US06967536B2 Phase-locked loop circuit reducing steady state phase error 有权
标题翻译：锁相环电路降低稳态相位误差
公开(公告)号：US06967536B2
公开(公告)日：2005-11-22
申请号：US10664884
申请日：2003-09-22
申请人： Keiji Hayashida , Atsushi Hasegawa
发明人： Keiji Hayashida , Atsushi Hasegawa
IPC分类号： H03L7/08 , H03L7/07 , H03L7/081 , H03L7/087 , H03L7/00
CPC分类号： H03L7/081 , H03L7/07 , H03L7/087
摘要： A phase-locked loop circuit has a DLL circuit in a stage preceding an analog PLL circuit. The DLL circuit detects a phase difference between a reference clock signal and a feedback signal, changes the detected phase difference to a phase difference increased so as to be greater than a steady state phase error which the analog PLL circuit has, and supplies the resultant phase difference to the analog PLL circuit. While the phase difference between the reference clock signal and the feedback signal is being detected by the DLL circuit, the analog PLL circuit operates to reduce the increased phase difference to the steady state phase error. As a result, the phase difference between the reference clock signal and the feedback signal is reduced to a sensitivity limit of a phase comparator in the DLL circuit.
摘要翻译：锁相环电路具有在模拟PLL电路之前的阶段中的DLL电路。 DLL电路检测参考时钟信号和反馈信号之间的相位差，将检测到的相位差改变为相位差增大，使其大于模拟PLL电路所具有的稳态相位误差，并将所得相位与模拟PLL电路的区别。当DLL电路正在检测参考时钟信号和反馈信号之间的相位差时，模拟PLL电路的作用是将相位差增加到稳态相位误差。结果，参考时钟信号和反馈信号之间的相位差减小到DLL电路中的相位比较器的灵敏度极限。

42. 发明申请

US20050190315A1 Liquid crystal display device 有权
标题翻译：液晶显示装置
公开(公告)号：US20050190315A1
公开(公告)日：2005-09-01
申请号：US10625722
申请日：2003-07-24
申请人： Hiroaki Asuma , Atsushi Hasegawa , Toshio Miyazawa
发明人： Hiroaki Asuma , Atsushi Hasegawa , Toshio Miyazawa
IPC分类号： G02F1/1333 , G02F1/133 , G02F1/1335 , G02F1/13357 , G02F1/1343 , G02F1/1345 , G02F1/136 , G02F1/1362 , G02F1/1368 , H01L21/3205
CPC分类号： G02F1/136209 , G02F1/133555 , G02F1/136213
摘要： A display devices which exhibits improved image qualities has a pair of substrates which sandwich a liquid crystal layer there between. On one of the substrates there are a plurality of video signal lines, a plurality of pixel electrodes which are arranged in a matrix array and to which video signals are supplied from the video signal lines, and a plurality of conductive layers, which are provided at positions where portions thereof overlap with the video signal lines by way of an insulation film. The respective conductive layers are electrically connected to respective video signal lines. Further, the conductive layer is able to prevent light irradiated from a backlight from leaking through a gap defined between two neighboring pixel electrodes.
摘要翻译：具有改善的图像质量的显示装置具有夹在其间的液晶层的一对基板。在其中一个基板上，存在多个视频信号线，多个像素电极，它们被排列成矩阵阵列，视频信号从视频信号线提供到该多个像素电极，并且多个导电层设置在其部分部分通过绝缘膜与视频信号线重叠。各导电层电连接到相应的视频信号线。此外，导电层能够防止从背光照射的光从两个相邻像素电极之间限定的间隙泄漏。

43. 发明授权

US06763034B1 Connection ports for interconnecting modules in an integrated circuit 有权
标题翻译：用于在集成电路中互连模块的连接端口
公开(公告)号：US06763034B1
公开(公告)日：2004-07-13
申请号：US09411828
申请日：1999-10-01
申请人： Andrew M. Jones , John A. Carey , Atsushi Hasegawa
发明人： Andrew M. Jones , John A. Carey , Atsushi Hasegawa
IPC分类号： H04L1266
CPC分类号： H04L49/102 , G06F15/7825 , H04L49/555
摘要： Connection ports for interconnecting functional modules in an integrated circuit are described. The connection ports provide enhanced functionality based around a common port primitive. This simplifies port design and selection and also allows a common packet protocol to be used for communication of packets across the packet router. In particular, there is improved functionality of target ports which allow out of order requests to be dealt with and out of order responses to be generated.
摘要翻译：描述用于在集成电路中互连功能模块的连接端口。连接端口基于公共端口原语提供增强的功能。这简化了端口设计和选择，并且还允许通用分组协议用于通过分组路由器的分组通信。特别地，改进了目标端口的功能，这些端口允许处理不及时的请求并产生无序响应。

44. 发明授权

US06735683B2 Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements 失效
标题翻译：具有分层内部总线结构的单片机具有将CPU与其他处理元件耦合的数据和地址信号线
公开(公告)号：US06735683B2
公开(公告)日：2004-05-11
申请号：US10264618
申请日：2002-10-04
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F1500
CPC分类号： H04W52/0229 , G06F15/7814 , Y02D10/12 , Y02D10/13 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

45. 发明授权

US06735304B2 Adaptive filter and echo canceller using the same 失效
标题翻译：自适应滤波器和回波消除器使用相同
公开(公告)号：US06735304B2
公开(公告)日：2004-05-11
申请号：US09796448
申请日：2001-03-02
申请人： Atsushi Hasegawa
发明人： Atsushi Hasegawa
IPC分类号： H04M908
CPC分类号： H04B3/23
摘要： An adaptive filter allowing rapid adaptation to a sudden and great change in a system to be estimated is disclosed A memory stores position information indicative of a signal block connected to each of M filter circuits and power information obtained from K filter coefficients generated by each of the M filter circuits. A valid/invalid block selector selects one as an invalid block from the M signal blocks connected to the M filter circuits and determines position information indicative of a selected signal block as an invalid block and a corresponding filter circuit that has been connected to the selected signal block. The position information indicative of the selected signal block is appended to a queue of a shift register and position information is output from a head of the queue. Based on the corresponding filter circuit and the position information received from the shift register, a matrix switch connecting M filter circuits and M signal blocks is controlled.
摘要翻译：一种自适应滤波器，其允许快速适应要估计的系统的突然和巨大变化。存储器存储指示连接到M个滤波器电路中的每一个的信号块的位置信息和从由K个滤波器电路中的每一个产生的K个滤波器系数获得的功率信息 M滤波电路。有效/无效块选择器从连接到M个滤波器电路的M个信号块中选择一个作为无效块，并将表示所选择的信号块的位置信息确定为无效块，以及已经连接到所选信号的相应的滤波器电路块。指示所选择的信号块的位置信息被附加到移位寄存器的队列，并且从队列的头部输出位置信息。基于相应的滤波电路和从移位寄存器接收的位置信息，控制连接M个滤波电路和M个信号块的矩阵开关。

46. 发明授权

US06600797B1 Phase frequency synchronism circuit and optical receiver 失效
标题翻译：相频同步电路和光接收机
公开(公告)号：US06600797B1
公开(公告)日：2003-07-29
申请号：US09517942
申请日：2000-03-03
申请人： Atsushi Hasegawa , Tetsuya Aoki , Takeshi Yamashita
发明人： Atsushi Hasegawa , Tetsuya Aoki , Takeshi Yamashita
IPC分类号： H03D324
CPC分类号： H03L7/095 , H03L7/087 , H03L7/0891 , H03L7/113 , H04L7/033
摘要： In order to solve the problem that since a loop filter constant suitable for asynchronous state cannot be selected in the conventional phase frequency synchronism circuit, it takes a long time to synchronize the input data and the clock signal from the asynchronous state, the present invention is to propose a phase frequency synchronism circuit including a phase comparator for generating a voltage according to the phase difference of the clock signal to the input signal, a frequency comparator for deciding if the frequency of the clock signal is higher or lower than the transmission rate of the input signal and generating a binary signal, a synchronous identifying unit for deciding if the input signal and the clock signal are synchronized in their phases and frequencies, a first switch that receives the output from the phase comparator and is closed and opened when the synchronous identifying unit decides that they are synchronized and not synchronized, respectively, a second switch that receives the output from the frequency comparator and is opened and closed when the synchronous identifying unit decides that they are synchronized and not synchronized, respectively, a loop filter that receives the outputs from the first and second switches, and a voltage controlled oscillator that oscillates on the basis of the output from the loop filter.
摘要翻译：为了解决由于在常规的相位频率同步电路中不能选择适合于异步状态的环路滤波器常数的问题，从异步状态同步输入数据和时钟信号需要很长时间，本发明是提出一种相位频率同步电路，该相位频率同步电路包括：相位比较器，用于根据时钟信号与输入信号的相位差产生电压;频率比较器，用于判定时钟信号的频率是否高于或低于输入信号并产生二进制信号，同步识别单元，用于判定输入信号和时钟信号是否在其相位和频率上同步;第一开关，其接收来自相位比较器的输出，并且当同步识别单元分别决定它们是同步的，而不是同步的在接收来自频率比较器的输出时，当同步识别单元分别决定它们同步并且不同步时，分别开启和关闭一个接收来自第一和第二开关的输出的环路滤波器和振荡的压控振荡器在循环滤波器的输出的基础上。

47. 发明授权

US06559997B1 Optical transmitter and optical transmitting apparatus using the same 有权
公开(公告)号：US06559997B1
公开(公告)日：2003-05-06
申请号：US09247809
申请日：1999-02-11
申请人： Shigeru Tokita , Atsushi Hasegawa , Takahiro Hamagishi
发明人： Shigeru Tokita , Atsushi Hasegawa , Takahiro Hamagishi
IPC分类号： H04B1004
CPC分类号： H04B10/504 , H04B10/564
摘要： An optical transmitter for use in an optical transmitting system based on PDS (Passive Double Star) technology, does not erroneously output an optical signal when the optical transmitter is powered on/off. The optical transmitter has a current source 1 for outputting a drive current having a magnitude corresponding to an input control signal, a Laser diode (LD) for generating an optical output signal based on the received drive current, a modulator 9 for controlling the supply and cutoff of the drive current to the Laser diode (LD), a source voltage detector 3 for monitoring a source voltage to detect whether the source voltage is lower than a predetermined voltage, and a switch circuit 4 for outputting a control signal to the current source 1 to stop the supply of the drive current when the source voltage is determined to be lower than the predetermined voltage.

48. 发明授权

US06477599B1 Data processing system and microcomputer 失效
标题翻译：数据处理系统和微机
公开(公告)号：US06477599B1
公开(公告)日：2002-11-05
申请号：US09186075
申请日：1998-11-05
申请人： Takaaki Suzuki , Tomoya Takasuga , Atsushi Hasegawa
发明人： Takaaki Suzuki , Tomoya Takasuga , Atsushi Hasegawa
IPC分类号： G06F1200
CPC分类号： G06F13/28
摘要： An input/output device used as a transfer request source outputs a data transfer set command for specifying each transfer channel, each transfer address, the number of transfers, etc. onto a bus together with a data transfer request without involving the use of the CPU. According to the data transfer set command, data transfer control information is set to direct memory access control means, and DMA transfer is started between the input/output device and a memory designated by the transfer address, for example. When the input/output device used as a data transfer request source desires to perform data transfer without regard to the state of processing by the microcomputer, it can perform data transfer processing with its own timing and the data transfer with the input/output device as a principal base is allowed.
摘要翻译：用作传送请求源的输入/输出设备输出数据传送设置命令，用于将数据传送通道，每个传送地址，传输次数等与数据传输请求一起输出到总线上，而不需要使用CPU 。根据数据传送设定命令，数据传送控制信息被设置为直接存储器访问控制装置，并且例如在输入/输出装置和由传送地址指定的存储器之间开始DMA传送。当用作数据传输请求源的输入/输出设备希望执行数据传输而不考虑微处理器的处理状态时，它可以利用其自身的定时和输入/输出设备的数据传输来执行数据传输处理，如主要基地是允许的。

49. 发明授权

US06381680B1 Data processing system with an enhanced cache memory control 失效
标题翻译：数据处理系统具有增强的高速缓存存储器控制
公开(公告)号：US06381680B1
公开(公告)日：2002-04-30
申请号：US09087900
申请日：1998-06-01
申请人： Tadahiko Nishimukai , Atsushi Hasegawa , Masaru Matsumura
发明人： Tadahiko Nishimukai , Atsushi Hasegawa , Masaru Matsumura
IPC分类号： G06F1200
CPC分类号： G06F9/30043 , G06F12/0888
摘要： A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) is for a part (such as a status register in the above-mentioned microcomputer system) accessible by another processing device, such as an I/O device, within the entire storage area (such as a main storage and the status register) accessible by the central processing system. If data to be fetched for an instruction executed by the central processing unit is not found in a cache memory, the data is fetched from the entire storage area. A write circuit is provided which writes the fetched data into the cache memory when the detect circuit shows that the access address is not for the part accessible by the other processing device within the entire storage area, but otherwise the write circuit does not write the fetched data into the cache memory.
摘要翻译：在诸如I / O映射微机系统的系统中提供检测电路，以便检测由中央处理单元（CPU）生成的读取访问请求的访问地址是否用于一部分（诸如状态在由中央处理系统可访问的整个存储区域（诸如主存储器和状态寄存器）内的另一处理设备（诸如I / O设备）可访问的上述微机系统中。如果在高速缓冲存储器中没有找到要由中央处理单元执行的指令取出的数据，则从整个存储区域取出数据。提供了一种写入电路，当检测电路显示存取地址不能由整个存储区域内的其他处理设备访问的部分时，将读取的数据写入高速缓冲存储器，但是写入电路不写入读取的数据数据进入缓存内存。

50. 发明授权

US06272596B1 Data processor 失效
标题翻译：数据处理器
公开(公告)号：US06272596B1
公开(公告)日：2001-08-07
申请号：US09396414
申请日：1999-09-15
申请人： Tadahiko Nishimukai , Atsushi Hasegawa , Kunio Uchiyama , Ikuya Kawasaki , Makoto Hanawa
发明人： Tadahiko Nishimukai , Atsushi Hasegawa , Kunio Uchiyama , Ikuya Kawasaki , Makoto Hanawa
IPC分类号： G06F1202
CPC分类号： G06F9/30047 , G06F9/30043 , G06F9/3802 , G06F9/3824 , G06F12/0848 , G06F12/0891
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has an output the instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executor executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
摘要翻译：用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器。当指令存在于第一关联存储器中时，数据处理器还包括从第一关联存储器读取指令的指令控制器，并且当指令不存在于第一关联存储器中时，从主存储器读取指令。控制器还具有要执行的指令的输出。指令执行单元具有存储从主存储器读出的操作数数据的第二关联存储器。当操作数数据存在于第二关联存储器中时，当操作数数据不存在于第二关联存储器中时，指令执行器通过使用从第二关联存储器读出的操作数数据执行指令。

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