专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US4392201A Diagnostic subsystem for a cache memory 失效
标题翻译：高速缓存的诊断子系统
公开(公告)号：US4392201A
公开(公告)日：1983-07-05
申请号：US221855
申请日：1980-12-31
申请人： Richard P. Brown , George J. Barlow , Arthur Peters
发明人： Richard P. Brown , George J. Barlow , Arthur Peters
IPC分类号： G06F12/08 , G11C29/26 , G06F13/00 , G06F13/06
CPC分类号： G06F12/0851 , G11C29/26
摘要： A cache memory wherein data words identified by odd address numbers are stored separately from data words identified by even address numbers. A group of diagnostic control registers supply signals for controlling the testing of the cache within the cache memory to determine the operability of the individual elements included in the cache memory.
摘要翻译：高速缓冲存储器，其中由奇数地址号码识别的数据字与偶数地址号码识别的数据字分开存储。一组诊断控制寄存器提供用于控制高速缓冲存储器内的高速缓存测试的信号，以确定包含在高速缓冲存储器中的各个元件的可操作性。

42. 发明授权

US4371928A Interface for controlling information transfers between main data processing systems units and a central subsystem 失效
标题翻译：用于控制主数据处理系统单元和中央子系统之间的信息传输的接口
公开(公告)号：US4371928A
公开(公告)日：1983-02-01
申请号：US140623
申请日：1980-04-15
申请人： George J. Barlow , Philip E. Stanley , Richard P. Brown
发明人： George J. Barlow , Philip E. Stanley , Richard P. Brown
IPC分类号： G06F12/06 , G06F12/04 , G06F13/16 , G06F13/36 , G06F13/00
CPC分类号： G06F12/04 , G06F13/1678
摘要： In a data processing system, a system memory includes first memory modules having a data path of a first bit width and second memory modules having a data path of a second bit width with the first bit width being less than the second bit width. A central subsystem includes a cache memory unit and processing units for initiating requests for data transfers of the second bit width between the system memory and the subsystem processing units. An interface coupling the system memory and the central subsystem for bidirectional data transfers generates, in response to a memory request of a second bit width wherein the requested data is stored in a first memory module, additional memory requests until sufficient data has been retrieved from the system memory to satisfy the central subsystem request. The interface also monitors data transfers between the system processing units and the system memory and transfers the data transfers to the central subsystem in order to update and to retain the integrity of the cache memory in the central subsystem.
摘要翻译：在数据处理系统中，系统存储器包括具有第一位宽度的数据路径的第一存储器模块和具有第二位宽度的数据路径的第二存储器模块，第一位宽小于第二位宽度。中央子系统包括高速缓冲存储器单元和处理单元，用于启动系统存储器和子系统处理单元之间的第二位宽的数据传输请求。耦合系统存储器和用于双向数据传输的中央子系统的接口响应于第二位宽度的存储器请求而产生其中所请求的数据存储在第一存储器模块中的附加存储器请求，直到从系统内存以满足中央子系统的要求。该接口还监视系统处理单元和系统存储器之间的数据传输，并将数据传输传送到中央子系统，以便更新并保持高速缓冲存储器在中央子系统中的完整性。

43. 发明授权

US4236209A Intersystem transaction identification logic 失效
标题翻译：系统事务识别逻辑
公开(公告)号：US4236209A
公开(公告)日：1980-11-25
申请号：US956389
申请日：1978-10-31
申请人： Ralph M. Lombardo, Jr. , George J. Barlow , John J. Bradley , Kenneth E. Bruce , John W. Conway , Bruce H. Tarbox
发明人： Ralph M. Lombardo, Jr. , George J. Barlow , John J. Bradley , Kenneth E. Bruce , John W. Conway , Bruce H. Tarbox
IPC分类号： G06F13/36 , G06F13/40 , G06F13/42 , G06F3/04 , G06F13/00
CPC分类号： G06F13/36 , G06F13/4027 , G06F13/4213
摘要： A logic system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein dedicated locations in a file register are selected at the bus rate in response to binary coded information received from a local communication bus. ISL transactions to be initiated in response to bus cycle requests thereby are identified. ISL transactions are handled in parallel, and memory transfers are segregated from non-memory transfers to avoid unnecessary delays in memory transfers.
摘要翻译：公开了一种在数据处理系统中在通信总线之间容纳二进制编码信息的传输的系统间链路（ISL）单元中的逻辑系统，其中文件寄存器中的专用位置响应于从本地通讯总线。识别出响应于总线周期请求发起的ISL事务。 ISL事务被并行处理，并且内存传输与非内存传输隔离，以避免内存传输中不必要的延迟。

44. 发明授权

US4234919A Intersystem communication link 失效
标题翻译：系统间通信链路
公开(公告)号：US4234919A
公开(公告)日：1980-11-18
申请号：US956385
申请日：1978-10-31
申请人： Kenneth E. Bruce , George J. Barlow , John W. Conway , Ralph M. Lombardo, Jr. , John J. Bradley , David B. O'Keefe
发明人： Kenneth E. Bruce , George J. Barlow , John W. Conway , Ralph M. Lombardo, Jr. , John J. Bradley , David B. O'Keefe
IPC分类号： G06F13/36 , G06F13/40 , G06F13/42 , G06F3/04
CPC分类号： G06F13/36 , G06F13/4027 , G06F13/4213
摘要： A logic system referred to as an intersystem link unit (ISL) is provided for accommodating the transfer of binary coded information between two or more communication busses in a data processing system, wherein information including memory and non-memory read and write requests, CPU to CPU interrupts, peripheral control units to CPU interrupts may be transferred between plural communication busses each supporting plural data processing units including plural CPUs without substantially affecting the bus rate of the individual communication busses. Binary coded information from a communication bus is acquired asynchronously, and plural bus communications of different types are accommodated in parallel. The ISL units further may be dynamically reconfigured to provide for a reallocation of communication bus resources between communication busses.
摘要翻译：被称为系统间链路单元（ISL）的逻辑系统被提供用于在数据处理系统中的两个或多个通信总线之间容纳二进制编码信息的传送，其中包括存储器和非存储器读写请求的信息，CPU到 CPU中断，外围控制单元到CPU中断可以在多个通信总线之间传送，每个通信总线支持包括多个CPU的多个数据处理单元，而不会显着影响各个通信总线的总线速率。来自通信总线的二进制编码信息被异步地获取，并且并行地容纳不同类型的多个总线通信。还可以动态地重新配置ISL单元以提供通信总线之间的通信总线资源的重新分配。

45. 发明授权

US4077565A Error detection and correction locator circuits 失效
标题翻译：误差检测和校正定位电路
公开(公告)号：US4077565A
公开(公告)日：1978-03-07
申请号：US727820
申请日：1976-09-29
申请人： Chester M. Nibby, Jr. , George J. Barlow
发明人： Chester M. Nibby, Jr. , George J. Barlow
IPC分类号： G06F11/10 , H03M13/19 , G11C29/00 , G06F11/12
CPC分类号： G06F11/1048 , H03M13/19
摘要： A main memory system includes encoder and decoder circuits. The encoder circuits are connected to receive data bits and parity bits and from them generate check code bits which are stored with the data bits during a write cycle of operation. The decoder circuits are connected to receive data and check bits read out from memory during a read cycle of operation. The decoder circuits include a plurality of decoder circuits and error locator circuits. Circuits via exclusive OR circuits generate a number of syndrome bit signals. These signals are divided into first and second groups. The first group is coded to specify which one of a number of decoder circuits comprising the error locator circuits is to be enabled in the case of an error condition. The second group of signals is coded to designate the particular data bit to be corrected by the decoder circuits. Predetermined output terminals of each of the decoder circuits representative of valid single bit data error conditions are applied to a plurality of correction circuits for modification of the data signals as specified by the decoder circuits. Additionally, signals from predetermined output terminals of certain ones of the decoder circuits representative of certain single check code bit error conditions are utilized for providing the correct parity for the data signals associated therewith.
摘要翻译：主存储器系统包括编码器和解码器电路。编码器电路被连接以接收数据位和奇偶校验位，并且从它们产生在操作的写周期期间与数据位一起存储的校验码位。在操作的读取周期期间，解码器电路被连接以接收从存储器读出的数据和校验位。解码器电路包括多个解码器电路和误差定位器电路。通过异或电路的电路产生多个校正子位信号。这些信号被分成第一组和第二组。第一组被编码以指定在错误状况的情况下启用包括错误定位器电路的多个解码器电路中的哪一个。第二组信号被编码以指定由解码器电路校正的特定数据位。代表有效的单位数据错误条件的每个解码器电路的预定输出端子被施加到由解码器电路指定的用于修改数据信号的多个校正电路。此外，代表某些单个校验码位错误条件的某些解码器电路的来自预定输出端的信号被用于为与其相关联的数据信号提供正确的奇偶校验。

46. 发明授权

US4072853A Apparatus and method for storing parity encoded data from a plurality of input/output sources 失效
标题翻译：用于存储来自多个输入/输出源的奇偶校验编码数据的装置和方法
公开(公告)号：US4072853A
公开(公告)日：1978-02-07
申请号：US727821
申请日：1976-09-29
申请人： George J. Barlow , Chester M. Nibby, Jr.
发明人： George J. Barlow , Chester M. Nibby, Jr.
IPC分类号： G06F11/10 , G11C29/00 , G06F11/12
CPC分类号： G06F11/1024 , G06F11/1056
摘要： Apparatus and method are included in the main memory of the data processing system which receives data from a plurality of input/output devices connected to a common bus. During a write cycle of operation, a device applies a plurality of data byte signals together with associated parity bits for writing into an addressed storage location of memory. Error detection and correction encoder circuits are connected to receive the data bits and parity bits and from them generate check code bits which are coded to signal selectively the presence of an uncorrectable error condition in accordance with the parity bits from a given source. During a read cycle of operation, error detection and correction decoder circuits connected to the memory in response to the data and check code bits read out from an addressed location are operative to generate a number of syndrome bits having a predetermined characteristic for indicating the existence of an uncorrectable error condition when the parity bits associated with data signals when written originally into memory if checked would have indicated that the data was in error.
摘要翻译：数据处理系统的主存储器中包括装置和方法，该数据处理系统从连接到公共总线的多个输入/输出装置接收数据。在操作的写周期期间，设备将多个数据字节信号与相关联的奇偶校验位一起应用以写入存储器的寻址存储位置。连接错误检测和校正编码器电路以接收数据位和奇偶校验位，并且从它们产生编码的校验码位，以根据来自给定源的奇偶校验位选择性地存在不可校正的错误状况。在操作的读取周期期间，响应于从寻址位置读出的数据和校验码位连接到存储器的错误检测和校正解码器电路可操作以产生具有预定特性的多个校正子位，用于指示存在当与最初写入存储器的数据信号相关联的奇偶校验位如果被检查时，将会出现数据错误的情况，这是一个不可校正的错误状态。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式