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41. 发明授权

US08174074B2 Asymmetric embedded silicon germanium field effect transistor 有权
标题翻译：非对称嵌入式硅锗场效应晶体管
公开(公告)号：US08174074B2
公开(公告)日：2012-05-08
申请号：US12551804
申请日：2009-09-01
申请人： Chung-Hsun Lin , Isaac Lauer , Jeffrey W. Sleight
发明人： Chung-Hsun Lin , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L27/12
CPC分类号： H01L29/78687 , H01L21/26586 , H01L29/6656 , H01L29/66636 , H01L29/66659 , H01L29/66742 , H01L29/7835 , H01L29/78612 , H01L29/78624
摘要： A semiconductor device, an integrated circuit, and method for fabricating the same are disclosed. The semiconductor device includes a gate stack formed on an active region of a silicon-on-insulator substrate. A gate spacer is formed over the gate stack. A source region that includes embedded silicon germanium is formed within the semiconductor layer. A drain region that includes embedded silicon germanium is formed within the semiconductor layer. The source region includes an angled implantation region that extends into the embedded silicon germanium of the source region, and is asymmetric relative to the drain region.
摘要翻译：公开了一种半导体器件，集成电路及其制造方法。半导体器件包括形成在绝缘体上硅衬底的有源区上的栅叠层。在栅极堆叠上形成栅极间隔物。在半导体层内形成包括嵌入硅锗的源区。在半导体层内形成包括嵌入硅锗的漏区。源极区域包括延伸到源极区域的嵌入式硅锗中的成角度的注入区域，并且相对于漏极区域是不对称的。

42. 发明授权

US08105893B2 Diffusion sidewall for a semiconductor structure 有权
标题翻译：用于半导体结构的扩散侧壁
公开(公告)号：US08105893B2
公开(公告)日：2012-01-31
申请号：US12621216
申请日：2009-11-18
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
IPC分类号： H01L21/8238
CPC分类号： H01L21/76224 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other.
摘要翻译：在半导体结构中形成扩散侧壁的方法和具有扩散侧壁的半导体结构的方法包括将沟槽蚀刻到半导体衬底中以形成第一和第二有源区，沿着有源硅区（RX ）去除沿着第一和第二有源区域之一的RX区域的暴露的侧壁形成的氧化物衬垫，通过在RX的暴露侧壁内外延生长原位掺杂材料来形成扩散侧壁区域，并且在第一和第二有源区域之间的沟槽内形成隔离区域，以将第一和第二有源区域彼此电隔离。

43. 发明申请

US20120007054A1 Self-Aligned Contacts in Carbon Devices 有权
标题翻译：碳装置中的自对准触点
公开(公告)号：US20120007054A1
公开(公告)日：2012-01-12
申请号：US12832224
申请日：2010-07-08
申请人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L29/76 , H01L29/78 , H01L27/12 , H01L29/24 , H01L21/86 , H01L21/04
CPC分类号： H01L29/1606 , B82Y10/00 , H01L29/165 , H01L29/41733 , H01L29/41766 , H01L29/41775 , H01L29/66431 , H01L29/66742 , H01L29/7781 , H01L29/78 , H01L29/78684 , H01L51/0048
摘要： A method for forming a semiconductor device includes forming a carbon material on a substrate, forming a gate stack on the carbon material, removing a portion of the substrate to form at least one cavity defined by a portion of the carbon material and the substrate, and forming a conductive contact in the at least one cavity.
摘要翻译：一种用于形成半导体器件的方法包括在基片上形成碳材料，在碳材料上形成栅叠层，去除基片的一部分以形成由碳材料和基片的一部分限定的至少一个空腔，以及在所述至少一个空腔中形成导电接触。

44. 发明申请

US20110248362A1 SELF-ALIGNED CONTACTS 有权
标题翻译：自对准联系人
公开(公告)号：US20110248362A1
公开(公告)日：2011-10-13
申请号：US12755752
申请日：2010-04-07
申请人： Dechao Guo , Wilfried E.A. Haensch , Shu-Jen Han , Chung-Hsun Lin
发明人： Dechao Guo , Wilfried E.A. Haensch , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L21/28008 , H01L21/28052 , H01L21/28097 , H01L21/76897 , H01L29/517 , H01L29/66507 , H01L29/66545
摘要： A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.
摘要翻译：提供了一种形成具有自对准接触的栅极结构的方法，并且包括将牺牲层和次级层顺序地沉积到设置在栅极结构的位置处的多晶硅上，封装牺牲层，第二层和聚 -Si，通过形成在次级层中的开口去除牺牲层，并在至少由牺牲层正式占据的空间内形成硅化物。

45. 发明申请

US20110215300A1 GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE 有权
标题翻译：基于GRAPHENE的三维集成电路设备
公开(公告)号：US20110215300A1
公开(公告)日：2011-09-08
申请号：US12719058
申请日：2010-03-08
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Ning Su
IPC分类号： H01L27/088 , H01L21/8256
CPC分类号： H01L27/0688 , H01L29/1606 , Y10S977/755
摘要： A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices.
摘要翻译：三维（3D）集成电路（IC）结构包括在衬底上形成的第一层石墨烯; 使用第一层石墨烯形成的一个或多个有源器件的第一级; 绝缘层，形成在一个或多个有源器件的第一级上; 在所述绝缘层上形成的第二层石墨烯; 以及使用第二层石墨烯形成的一个或多个有源器件的第二电平，一个或多个有源器件的第二电平与一个或多个有源器件的第一电平电互连。

46. 发明申请

US20110163380A1 Body-Tied Asymmetric N-Type Field Effect Transistor 有权
标题翻译：体态不对称N型场效应晶体管
公开(公告)号：US20110163380A1
公开(公告)日：2011-07-07
申请号：US12683634
申请日：2010-01-07
申请人： Jeffrey W. Sleight , Chung-Hsun Lin , Josephine B. Chang , Leland Chang
发明人： Jeffrey W. Sleight , Chung-Hsun Lin , Josephine B. Chang , Leland Chang
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/1083 , H01L29/42384 , H01L29/66659 , H01L29/66772 , H01L29/78615
摘要： In one exemplary embodiment of the invention, an asymmetric N-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric N-type field effect transistor is operable to act as a symmetric N-type field effect transistor.
摘要翻译：在本发明的一个示例性实施例中，非对称N型场效应晶体管包括：源极区，经由沟道耦合到漏极区; 覆盖所述通道的至少一部分的栅极结构; 至少部分地设置在所述通道中的卤素植入物，其中所述晕轮植入物设置成比所述漏极区域更靠近所述源极区域; 以及耦合到该通道的机身连接。在另一示例性实施例中，非对称N型场效应晶体管可用作对称N型场效应晶体管。

47. 发明申请

US20110049627A1 EMBEDDED SILICON GERMANIUM N-TYPE FILED EFFECT TRANSISTOR FOR REDUCED FLOATING BODY EFFECT 有权
标题翻译：嵌入式硅锗锗型N型透明效应晶体管，用于降低浮体效应
公开(公告)号：US20110049627A1
公开(公告)日：2011-03-03
申请号：US12551941
申请日：2009-09-01
申请人： LELAND CHANG , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： LELAND CHANG , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/8238 , H01L29/66636 , H01L29/66772 , H01L29/78618 , H01L29/78621
摘要： A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively.
摘要翻译：一种制造半导体器件的方法包括在绝缘体上硅衬底的有源区上形成栅叠层。有源区在半导体层内并掺杂有p型掺杂剂。围绕栅极堆叠形成栅极间隔物。在为源极区域保留的区域中形成第一沟槽，并且在为漏极区域保留的区域中形成第二沟槽。形成第一和第二沟槽，同时保持暴露为源极区域保留的区域和为漏极区域保留的区域。硅锗外延生长在第一沟槽和第二沟槽内，同时保持分别保留用于源区和漏区的区域。

48. 发明授权

US09041057B2 Field effect transistor device with shaped conduction channel 有权
标题翻译：具有形状导通通道的场效应晶体管器件
公开(公告)号：US09041057B2
公开(公告)日：2015-05-26
申请号：US13551164
申请日：2012-07-17
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L29/78 , H01L29/10 , H01L29/165 , H01L29/423 , H01L29/66
CPC分类号： H01L29/78 , H01L29/1037 , H01L29/1054 , H01L29/165 , H01L29/4236 , H01L29/66621
摘要： A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.
摘要翻译：场效应晶体管器件包括衬底，设置在衬底上的硅锗（SiGe）层，衬在由衬底和硅锗层限定的空腔的表面上的栅介质层，栅极介电层上的金属栅极材料，填充空腔的金属栅极材料，源极区域和漏极区域。

49. 发明授权

US08877593B2 Semiconductor device including an asymmetric feature, and method of making the same 有权
标题翻译：包括非对称特征的半导体器件及其制造方法
公开(公告)号：US08877593B2
公开(公告)日：2014-11-04
申请号：US13194980
申请日：2011-07-31
申请人： Josephine Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey Sleight
发明人： Josephine Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey Sleight
IPC分类号： H01L21/336 , H01L29/417 , H01L29/66 , H01L29/78 , H01L27/088 , H01L21/8238 , H01L21/8234 , H01L21/66
CPC分类号： H01L29/7835 , H01L21/823425 , H01L21/823475 , H01L21/823814 , H01L21/823871 , H01L27/088 , H01L29/41775 , H01L29/66659 , H01L29/7845
摘要： A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact.
摘要翻译：具有不对称特征的半导体器件（例如，场效应晶体管（FET））包括形成在衬底上的第一栅极，形成在第一栅极一侧的衬底中的第一和第二扩散区域以及第一和第二触点，分别与第一和第二扩散区接触，第一触点相对于第二触点是不对称的。

50. 发明授权

US08823064B2 Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure 有权
标题翻译：通过使用可变间距门形成的非对称FET用作逻辑器件和测试结构
公开(公告)号：US08823064B2
公开(公告)日：2014-09-02
申请号：US13441048
申请日：2012-04-06
申请人： Josephine B. Chang , Chung-Hsun Lin , Isaac Lauer , Jeffrey W. Sleight
发明人： Josephine B. Chang , Chung-Hsun Lin , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L27/12
CPC分类号： H01L27/088 , H01L21/823437 , H01L22/34 , H01L27/0207 , H01L27/1203
摘要： Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a FET device is provided. The FET device includes a wafer; a plurality of active areas formed in the wafer; a plurality of gate stacks on the wafer, wherein at least one of the gate stacks is present over each of the active areas, and wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area; spacers on opposite sides of the gate stacks; and an angled implant in the source side of the given active area.
摘要翻译：提供了非对称FET器件及其制造方法，其采用可变间距栅极。一方面，提供一种FET器件。 FET器件包括晶片; 形成在晶片中的多个有源区; 晶片上的多个栅极堆叠，其中至少一个栅极堆叠存在于每个有源区域上，并且其中栅极堆叠具有不规则的栅极至栅极间隔，使得对于至少一个有源区域在给定有源区域的源极侧上的栅极至栅极间隔大于给定有源区域的漏极侧上的栅极至栅极间隔; 栅极堆叠的相对侧上的间隔物; 以及在给定活动区域的源侧的成角度的植入物。

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