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    • 41. 发明授权
    • Post-CMP-Cu deposition and CMP to eliminate surface voids
    • 后CMP-Cu沉积和CMP以消除表面空隙
    • US06403466B1
    • 2002-06-11
    • US09805651
    • 2001-03-13
    • Sergey D. Lopatin
    • Sergey D. Lopatin
    • H01L214763
    • H01L21/7684H01L21/76877
    • A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A seed layer is deposited over the barrier layer and a conductor core is deposited over the seed layer, filling the opening of in the channel dielectric layer. The seed and barrier layers are then removed above the dielectric layer. A conductive layer is then deposited, filling any voids or depressions in the conductor core, and is subsequently removed above the dielectric layer resulting in a conductive channel of uniform thickness.
    • 提供了一种具有半导体器件的半导体衬底的集成电路的制造方法。 在半导体衬底上形成器件电介质层。 器件电介质层上的沟道电介质层具有形成在其中的开口。 屏障层对通道开口进行排列。 种子层沉积在阻挡层上,并且导体芯沉积在种子层上,填充沟道介电层的开口。 然后在电介质层上方去除种子和阻挡层。 然后沉积导电层,填充导体芯中的任何空隙或凹陷,并且随后在电介质层上方移除,导致均匀厚度的导电沟道。