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41. 发明申请

US20070135957A1 Model generating apparatus, model generating system, and fault detecting apparatus 审中-公开
标题翻译：模型生成装置，模型生成系统和故障检测装置
公开(公告)号：US20070135957A1
公开(公告)日：2007-06-14
申请号：US11606383
申请日：2006-11-30
申请人： Makoto Ogawa , Toshikazu Nakamura , Yoshikazu Aikawa , Shigeru Obayashi
发明人： Makoto Ogawa , Toshikazu Nakamura , Yoshikazu Aikawa , Shigeru Obayashi
IPC分类号： G06F19/00
CPC分类号： G05B19/41875 , G05B17/02 , G05B23/0243 , G05B2219/31357 , Y02P90/22
摘要： A model generating apparatus includes: a first input device for inputting process state information; a second input device for inputting test result information; a characteristic quantity extracting device for extracting a process characteristic quantity from the process state information in each of the areas; and an analyzing device for generating a process-quality model by executing an analysis of data mining using the process characteristic quantity and the test result information associated with each other. The model generating apparatus further includes: a third input device for inputting process position information so that the process position information can be associated with the process state information; and a fourth input device for inputting test position information so that the test position information can be associated with test result information.
摘要翻译：模型生成装置包括：用于输入处理状态信息的第一输入装置; 用于输入测试结果信息的第二输入设备; 特征量提取装置，用于从每个区域中的处理状态信息中提取处理特征量; 以及分析装置，用于通过使用相关联的处理特征量和测试结果信息执行数据挖掘的分析来生成过程质量模型。模型生成装置还包括：第三输入装置，用于输入处理位置信息，使得处理位置信息可以与处理状态信息相关联; 以及第四输入装置，用于输入测试位置信息，使得测试位置信息可以与测试结果信息相关联。

42. 发明授权

US07126522B2 Apparatus and method of analog-to-digital conversion 失效
标题翻译：模数转换的装置和方法
公开(公告)号：US07126522B2
公开(公告)日：2006-10-24
申请号：US11090192
申请日：2005-03-28
申请人： Makoto Ogawa
发明人： Makoto Ogawa
IPC分类号： H03M1/12
CPC分类号： H03M1/1225
摘要： An analog-to-digital conversion apparatus includes a register group, a selecting section and an A/D conversion section. The register group has a plurality of registers holding a plurality of channel specification data, respectively. The selecting section is connected with a plurality of analog channels, and sequentially selects the plurality of analog channels for analog-to-digital (A/D) conversion continuously without any idling time based on the plurality of channel specification data held by the plurality of registers. The A/D conversion section carries out the A/D conversion of an analog signal on each of the analog channels selected by the selecting section into a digital signal.
摘要翻译：模数转换装置包括寄存器组，选择部分和A / D转换部分。寄存器组具有分别保持多个通道指定数据的多个寄存器。选择部分与多个模拟通道连接，并且基于由多个模拟通道保持的多个通道指定数据，连续地依次选择用于模数（A / D）转换的多个模拟通道，而没有任何空转时间注册 A / D转换部分对由选择部分选择的每个模拟信道上的模拟信号进行A / D转换为数字信号。

43. 发明申请

US20050159835A1 Device for and method of creating a model for determining relationship between process and quality 审中-公开
标题翻译：创建用于确定过程和质量之间关系的模型的设备和方法
公开(公告)号：US20050159835A1
公开(公告)日：2005-07-21
申请号：US11021112
申请日：2004-12-23
申请人： Kentaro Yamada , Yukihiro Aoyama , Makoto Ogawa , Toshikazu Nakamura , Yoshikazu Aikawa
发明人： Kentaro Yamada , Yukihiro Aoyama , Makoto Ogawa , Toshikazu Nakamura , Yoshikazu Aikawa
IPC分类号： G05B19/418 , C23C14/34 , G05B23/02 , G06F17/30 , G06F19/00 , G06G7/48 , G06Q50/00 , G06Q50/04 , H01L21/00 , H01L21/02 , H01L21/66 , H04L9/00
CPC分类号： G06Q10/06
摘要： A model creating device inputs process status data that are obtained in time series during a period during which each of process steps of a process is carried out and are related to status of this process, as well as inspection result data related to object articles that were processed by said process. An extracting part extracts a characteristic quantity from the process status data for every unit object article and for every process step. An analyzing part carries out an analysis by data mining by using the characteristic quantities and inspection result data in correlation with the unit object articles and creates a process-quality model that shows a relationship between the correlated characteristic quantities and inspection result data.
摘要翻译：模型创建装置输入在过程的每个处理步骤被执行并且与该过程的状态相关的时段期间以时间序列获得的过程状态数据以及与对象物品相关的检查结果数据由所述过程处理。提取部分从每个单位物品的处理状态数据和每个处理步骤中提取特征量。分析部分通过使用与单位对象物品相关的特征量和检查结果数据进行数据挖掘分析，并创建显示相关特征量与检验结果数据之间的关系的过程质量模型。

44. 发明授权

US06201810B1 High-speed routing control system 失效
标题翻译：高速路由控制系统
公开(公告)号：US06201810B1
公开(公告)日：2001-03-13
申请号：US08910117
申请日：1997-08-13
申请人： Michio Masuda , Motoo Nishihara , Makoto Ogawa
发明人： Michio Masuda , Motoo Nishihara , Makoto Ogawa
IPC分类号： H04L1256
CPC分类号： H04L45/04 , H04L45/22 , H04L45/70
摘要： In a high-speed routing control system, plural path candidates each leading to a destination node are selected on the basis of physical connection information of links connecting respective nodes in a path candidate selection unit 11, and a path candidate containing no congestion-occurring link is specified as the optimum path from the plural path candidates selected by the path candidate selection unit 11 in an optimizing unit 12. Accordingly, even when the destination node is nearer to the self node, the optimum path selection can be performed, and a switching operation to a bypass path can be performed at high speed. In addition, the traffic amount based on topology information can be suppressed, and the large-scaling of the network can be supported.
摘要翻译：在高速路由选择控制系统中，根据路径候补选择部11中连接各节点的链路的物理连接信息和不包含拥塞发生链路的路径候选，选择各个通向目的地节点的路径候选被指定为在优化单元12中由路径候选选择单元11选择的多路径候选的最佳路径。因此，即使当目的地节点更靠近自身节点时，也可以执行最佳路径选择，并且切换可以高速地执行到旁路路径的操作。此外，可以抑制基于拓扑信息的流量，并且可以支持网络的大规模化。

45. 发明授权

US09704649B2 Method for producing ceramic electronic component 有权
公开(公告)号：US09704649B2
公开(公告)日：2017-07-11
申请号：US13105926
申请日：2011-05-12
申请人： Junichi Saito , Toshihiko Kobayashi , Makoto Ogawa , Akihiro Motoki , Kenichi Kawasaki , Tatsuo Kunishi
发明人： Junichi Saito , Toshihiko Kobayashi , Makoto Ogawa , Akihiro Motoki , Kenichi Kawasaki , Tatsuo Kunishi
IPC分类号： B05D5/12 , H01G2/10 , H01G4/224 , B05D7/14 , B05D1/38
CPC分类号： H01G2/103 , B05D1/38 , B05D5/12 , B05D7/14 , H01G4/224
摘要： In order to prevent the ingress of moisture into a void section of a component main body of a ceramic electronic component, at least the component main body of the ceramic electronic component is provided with water repellency using a water repellent agent. The water repellent agent is dissolved in a supercritical fluid such as, a supercritical CO2 fluid, as a solvent to provide at least the component main body with water repellency. After providing the water repellency, the water repellent agent on the outer surface of the component main body is removed. As the water repellent agent, a silane coupling agent may be used.

46. 发明授权

US09123469B2 Laminated ceramic electronic component and manufacturing method therefor 有权
标题翻译：层压陶瓷电子元件及其制造方法
公开(公告)号：US09123469B2
公开(公告)日：2015-09-01
申请号：US13050977
申请日：2011-03-18
申请人： Akihiro Motoki , Syunsuke Takeuchi , Makoto Ogawa , Seiichi Nishihara , Kenichi Kawasaki , Shuji Matsumoto
发明人： Akihiro Motoki , Syunsuke Takeuchi , Makoto Ogawa , Seiichi Nishihara , Kenichi Kawasaki , Shuji Matsumoto
IPC分类号： H01G4/005 , H01G4/228 , H01G4/12 , H01G4/30
CPC分类号： H01G4/248 , B32B18/00 , B32B37/18 , B32B2307/202 , B32B2315/02 , B32B2457/00 , C23C18/40 , H01G4/005 , H01G4/012 , H01G4/12 , H01G4/228 , H01G4/30
摘要： In a method of forming a plating layer for an external terminal electrode by applying, for example, copper plating to an end surface of a component main body with respective ends of internal electrodes exposed, and then applying a heat treatment at a temperature of about 1000° C. or more in order to improve the adhesion strength and moisture resistance of the external terminal electrode, the plating layer may be partially melted to decrease the bonding strength of the plating layer. In the step of applying a heat treatment at a temperature of about 1000° C. or more to a component main body with plating layers formed thereon, the average rate of temperature increase from room temperature to the temperature of about 1000° C. or more is set to about 100° C./minute or more. This average rate of temperature increase maintains a moderate eutectic state in the plating layer and ensures a sufficient bonding strength of the plating layer.
摘要翻译：在形成外部端子电极用镀层的方法中，例如通过对内部电极的两端露出的部件主体的端面进行镀铜，然后在约1000℃的温度下进行热处理 ℃以上，为了提高外部端子电极的粘合强度和耐湿性，可以使镀层部分熔融，降低镀层的接合强度。在其上形成有镀层的组件主体上，在约1000℃以上的温度下进行热处理的步骤中，平均温度从室温升高至约1000℃以上的温度设定为约100℃/分钟以上。该平均升温速率在镀层中保持中等的共晶状态，并确保镀层的充分的接合强度。

47. 发明授权

US09111690B2 Multilayer electronic component 有权
标题翻译：多层电子元件
公开(公告)号：US09111690B2
公开(公告)日：2015-08-18
申请号：US12543549
申请日：2009-08-19
申请人： Akihiro Motoki , Makoto Ogawa , Toshiyuki Iwanaga , Akihiro Yoshida , Takayuki Kayatani
发明人： Akihiro Motoki , Makoto Ogawa , Toshiyuki Iwanaga , Akihiro Yoshida , Takayuki Kayatani
IPC分类号： H01G4/30 , H01G4/232 , H01C1/148 , H01C7/18
CPC分类号： H01G4/2325 , H01C1/148 , H01C7/18 , H01G4/30 , Y10T29/435
摘要： A method is used to manufacture a multilayer electronic component including a multilayer composite including internal electrodes having ends that are exposed at a predetermined surface of the multilayer composite. In the method, the exposed ends of the internal electrodes are coated with a metal film primarily composed of at least one metal selected from the group consisting of Pd, Au, Pt and Ag and having a thickness of at least about 0.1 μm by immersing the multilayer composite in a liquid containing a metal ion or a metal complex. Then, a continuous plating layer is formed by depositing a plating metal on the ends of the internal electrodes exposed at the predetermined surface of the multilayer composite, and subsequently growing the deposits of the plating metal so as to be connected to each other. Thus, exposed ends of the internal electrodes are electrically connected to each other.
摘要翻译：一种方法用于制造包括多层复合材料的多层电子部件，所述多层复合材料包括具有在所述多层复合材料的预定表面露出的端部的内部电极。在该方法中，内部电极的露出端涂覆有主要由选自Pd，Au，Pt和Ag的至少一种金属的金属膜，并且具有至少约0.1μm的厚度，通过将在含有金属离子或金属络合物的液体中的多层复合材料。然后，通过在暴露于多层复合材料的预定表面的内部电极的端部上沉积电镀金属，随后使电镀金属的沉积物彼此连接而形成连续镀层。因此，内部电极的露出端彼此电连接。

48. 发明授权

US08633636B2 Laminated ceramic electronic component and manufacturing method thereof 有权
标题翻译：层压陶瓷电子部件及其制造方法
公开(公告)号：US08633636B2
公开(公告)日：2014-01-21
申请号：US13189636
申请日：2011-07-25
申请人： Toshiyuki Iwanaga , Makoto Ogawa
发明人： Toshiyuki Iwanaga , Makoto Ogawa
IPC分类号： H01L21/20 , H01L41/047 , H01L41/083
CPC分类号： H01G4/30 , H01G4/012 , H01G4/12 , H01G4/232 , Y10T29/42
摘要： In a method for manufacturing a laminated ceramic electronic component, when a plating film to define an external terminal electrode is formed by plating exposed ends of a plurality of internal electrodes at a WT surface of a component main body, ingress of a plating solution may be caused from a gap between an end edge of the plating film and the component main body to decrease the reliability of a laminated electronic component obtained. An internal dummy electrode is provided around a region where the exposed ends of the plurality of internal electrodes are distributed in the WT surface of the component main body. The internal dummy electrode includes two LW-direction sections extending parallel or substantially parallel to each other in a direction along the LW surface, and two LT-direction sections extending parallel or substantially parallel to each other in a direction along the LT surface. The plating film is formed at least over the exposed end of the internal dummy electrode. The internal dummy electrode is formed by wrapping an outer layer sheet with the internal dummy electrode formed around a laminate composed of ceramic layers and the internal electrodes.
摘要翻译：在层叠陶瓷电子部件的制造方法中，当通过在组件主体的WT表面上镀覆多个内部电极的露出端来形成限定外部端子电极的镀膜时，电镀液的入射可以是由镀膜的端部边缘与部件主体之间的间隙引起，从而降低了获得的层叠电子部件的可靠性。在多个内部电极的露出端分布在构件主体的WT面内的区域周围设置有内部虚设电极。内部虚拟电极包括沿着LW表面的方向彼此平行或基本平行延伸的两个LW方向部分和沿着LT表面的方向彼此平行或基本平行延伸的两个LT方向部分。至少在内部虚拟电极的露出端上形成镀膜。内部虚拟电极通过将外层片材包裹在由陶瓷层和内部电极构成的层叠体周围形成的内部虚拟电极而形成。

49. 发明授权

US08630080B2 Electronic component 有权
标题翻译：电子元器件
公开(公告)号：US08630080B2
公开(公告)日：2014-01-14
申请号：US13411752
申请日：2012-03-05
申请人： Toshiyuki Iwanaga , Makoto Ogawa , Masahito Saruban
发明人： Toshiyuki Iwanaga , Makoto Ogawa , Masahito Saruban
IPC分类号： H01G4/002
CPC分类号： H01G4/005
摘要： An electronic component that is prevented from being inclined with respect to a circuit board during and after mounting includes a laminated body that is preferably configured by stacking a plurality of insulator layers, and includes a lower surface with depressions provided thereon. The lower surface includes a series of outer edges of the insulator layers. Capacitor electrodes are defined by internal conductors incorporated in the laminated body, which respectively have exposed sections that are exposed from between the insulator layers in the depressions on the lower surface. External electrodes, which are preferably formed directly by plating, are provided in the depressions to cover the exposed sections.
摘要翻译：防止在安装期间和之后相对于电路板倾斜的电子部件包括优选地通过堆叠多个绝缘体层而构造的层叠体，并且包括设置有凹部的下表面。下表面包括绝缘体层的一系列外边缘。电容器电极由结合在层叠体中的内部导体限定，分别具有从下表面上的凹部中的绝缘体层之间露出的暴露部分。优选通过电镀直接形成的外部电极设置在凹部中以覆盖暴露部分。

50. 发明授权

US08587919B2 Laminate type ceramic electronic component and manufacturing method therefor 有权
标题翻译：层压陶瓷电子元件及其制造方法
公开(公告)号：US08587919B2
公开(公告)日：2013-11-19
申请号：US13208393
申请日：2011-08-12
申请人： Makoto Ogawa , Akihiro Motoki , Takehisa Sasabayashi , Takayuki Kayatani
发明人： Makoto Ogawa , Akihiro Motoki , Takehisa Sasabayashi , Takayuki Kayatani
IPC分类号： H01G4/30
CPC分类号： H01G4/005 , H01G4/30
摘要： In a laminate type ceramic electronic component, when an external electrode for a laminated ceramic capacitor is formed directly by plating onto a surface of a component main body, the film that is directly plated may have a low fixing strength with respect to the component main body. As the external electrode, a first plating layer composed of a Ni—P plating film with a P content rate of about 9 weight % or more is first formed such that a plating deposition deposited with the exposed ends of respective internal electrodes as starting points is grown on at least an end surface of a component main body. Then, a second plating layer composed of a Ni plating film containing substantially no P is formed on the first plating layer. Preferably, the first plating layer is formed by electroless plating, whereas the second plating layer is formed by electrolytic plating.
摘要翻译：在层叠型陶瓷电子部件中，当通过电镀直接形成在组件主体的表面上的层叠陶瓷电容器的外部电极时，直接镀膜的膜相对于部件主体可具有低的固定强度。作为外部电极，首先形成由P含量为约9重量％以上的Ni-P镀膜构成的第一镀层，以使各个内部电极的露出端作为起点沉积的电镀沉积为在组件主体的至少一个端面上生长。然后，在第一镀层上形成由基本上不含P的Ni镀膜构成的第二镀层。优选地，通过无电镀形成第一镀层，而通过电解电镀形成第二镀层。

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