会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 41. 发明申请
    • Transistor, method for manufacturing thereof, substrate for an electrooptical device
    • 晶体管及其制造方法,电光装置用基板
    • US20060214239A1
    • 2006-09-28
    • US11363994
    • 2006-03-01
    • Hiroyuki Shimada
    • Hiroyuki Shimada
    • H01L29/76H01L21/336
    • H01L29/78621H01L21/26586H01L29/66757H01L29/78666
    • Aspects of the invention can provide a transistor that can include a supporting substrate, a semiconductor film formed on an underlying insulating film provided on the supporting substrate and including a channel region and source and drain regions, and a gate electrode provided above the channel region. The semiconductor film can include a lightly doped region in which an impurity is injected at a low concentration between the channel region and the source and drain regions. The source and drain regions can include a heavily doped region in which an impurity is injected at a higher concentration than the lightly doped region. At least part of the lightly doped region provided along an inner wall of a groove can be provided on the supporting substrate.
    • 本发明的方面可以提供一种晶体管,其可以包括支撑衬底,形成在设置在支撑衬底上并包括沟道区域和源极和漏极区域的下面的绝缘膜上的半导体膜,以及设置在沟道区域上方的栅电极。 半导体膜可以包括在沟道区域和源极和漏极区域之间以低浓度注入杂质的轻掺杂区域。 源区和漏区可以包括其中以比轻掺杂区更高的浓度注入杂质的重掺杂区。 沿着槽的内壁设置的轻掺杂区域的至少一部分可以设置在支撑衬底上。
    • 43. 发明授权
    • Semiconductor device containing local interconnection and method of manufacturing the same
    • 包含本地互连的半导体器件及其制造方法
    • US06255701B1
    • 2001-07-03
    • US09070235
    • 1998-04-30
    • Hiroyuki Shimada
    • Hiroyuki Shimada
    • H01L2976
    • H01L27/11H01L21/76895H01L21/823835H01L21/823871H01L23/535H01L27/092H01L27/1108H01L2924/0002H01L2924/00
    • A semiconductor device has a local interconnecting part (20) for electrically connecting a silicon-containing first layer (12) and silicon-containing second layer (16). The local interconnecting part has a first metal silicide layer (22a) formed in a self-aligning manner on a surface of the first layer, a second metal silicide layer (22b) formed in a self-aligning manner on a surface of the second layer, and an interconnecting part for electrically connecting the first metal silicide layer and the second metal silicide layer. The interconnecting part has a single or a plurality of metallic layers (27), or a barrier layer (24) formed in contact with at least the first and second metal silicide layers, and a conductive layer (26) having a lower resistance than the barrier layer. In the semiconductor device, since impurities are hardly diffused in the metal or the barrier layer which constitutes the interconnecting part, the concentration of impurities in a layer with a defined silicon concentration, for example, in a source or drain region of a MOS element, does not vary, thus eliminating variation in the threshold value due to counter doping and increase in junction leak due to a decrease in impurity concentration. Since the interconnecting part has the conductive layer composed of a metal with high conductivity, the electrical resistance can be decreased, as compared with a conventional titanium nitride layer.
    • 半导体器件具有用于电连接含硅第一层(12)和含硅第二层(16)的局部互连部分(20)。 局部互连部分具有在第一层的表面上以自对准的方式形成的第一金属硅化物层(22a),在第二层的表面上以自对准的方式形成的第二金属硅化物层(22b) 以及用于电连接第一金属硅化物层和第二金属硅化物层的互连部分。 互连部分具有单个或多个金属层(27)或形成为与至少第一和第二金属硅化物层接触形成的阻挡层(24),以及具有比该第二金属硅化物层更低的电阻的导电层(26) 阻挡层。 在半导体器件中,由于杂质几乎不扩散到构成互连部件的金属或阻挡层中,所以在MOS元件的源极或漏极区域中具有规定的硅浓度的层中的杂质浓度, 不会发生变化,从而消除了由于反掺杂引起的阈值的变化,并且由于杂质浓度的降低而引起的结漏增加。 由于互连部分具有由具有高导电性的金属构成的导电层,因此与常规的氮化钛层相比可以降低电阻。