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41. 发明授权

US08130571B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08130571B2
公开(公告)日：2012-03-06
申请号：US13162180
申请日：2011-06-16
申请人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
发明人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
IPC分类号： G11C7/00
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior In a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.
摘要翻译：半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写非易失性存储区域。非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以不利于保证重写操作的次数; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数更多。

42. 发明授权

US08050085B2 Semiconductor processing device and IC card 有权
标题翻译：半导体处理装置和IC卡
公开(公告)号：US08050085B2
公开(公告)日：2011-11-01
申请号：US10521553
申请日：2002-08-29
申请人： Masatoshi Takahashi , Takanori Yamazoe , Kozo Katayama , Toshihiro Tanaka , Yutaka Shinagawa , Hiroshi Watase , Takeo Kanai , Nobutaka Nagasaki
发明人： Masatoshi Takahashi , Takanori Yamazoe , Kozo Katayama , Toshihiro Tanaka , Yutaka Shinagawa , Hiroshi Watase , Takeo Kanai , Nobutaka Nagasaki
IPC分类号： G11C7/10 , G11C11/40
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/40975 , G07F7/084 , G11C11/005 , G11C16/0425 , G11C16/0433 , G11C16/16
摘要： A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately. Therefore, the stored information can efficiently be erased before the execution of a processing of writing the program, and the stored information can be erased corresponding to the data length of a necessary processing unit in the write of the encryption key to be utilized in the calculation processing of the CPU.
摘要翻译：根据本发明的半导体处理装置包括用于擦除第一数据长度单元上存储的信息的第一非易失性存储器（21），用于擦除第二数据长度单元上存储的信息的第二非易失性存储器（22），以及中央处理单元（2），能够从/向外部输入/输出加密数据。第一非易失性存储器用于存储要用于加密数据的加密密钥。第二非易失性存储器用于存储要由中央处理单元处理的程序。用于存储程序和用于存储加密密钥的非易失性存储器彼此分离，并且存储在非易失性存储器中的信息的擦除单元的数据长度被分开地定义。因此，在执行写入程序的处理之前可以有效地擦除存储的信息，并且可以根据在计算中要使用的加密密钥的写入中的必要处理单元的数据长度来擦除存储的信息处理CPU。

43. 发明申请

US20110246860A1 Semiconductor Integrated Circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20110246860A1
公开(公告)日：2011-10-06
申请号：US13162180
申请日：2011-06-16
申请人： Yutaka SHINAGAWA , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
发明人： Yutaka SHINAGAWA , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
IPC分类号： H03M13/05 , G11C16/04 , G06F11/10
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior In a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.
摘要翻译：半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写非易失性存储区域。非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以不利于保证重写操作的次数; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数更多。

44. 发明授权

US07978545B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07978545B2
公开(公告)日：2011-07-12
申请号：US12775377
申请日：2010-05-06
申请人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
发明人： Yutaka Shinagawa , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
IPC分类号： G11C7/00
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.
摘要翻译：半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以在保证重写操作次数方面较差; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数更多。

45. 发明申请

US20100220531A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20100220531A1
公开(公告)日：2010-09-02
申请号：US12775377
申请日：2010-05-06
申请人： YUTAKA SHINAGAWA , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
发明人： YUTAKA SHINAGAWA , Takeshi Kataoka , Eiichi Ishikawa , Toshihiro Tanaka , Kazumasa Yanagisawa , Kazufumi Suzukawa
IPC分类号： G11C16/04 , G06F12/02 , G06F11/00 , G06F13/20
CPC分类号： G11C16/349 , G11C16/06 , G11C16/3495
摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.
摘要翻译：半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以在保证重写操作次数方面较差; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数更多。

46. 发明申请

US20100160206A1 SURFACTANT COMPOSITION 有权
标题翻译：表面活性剂组合物
公开(公告)号：US20100160206A1
公开(公告)日：2010-06-24
申请号：US12601214
申请日：2008-07-09
申请人： Keisuke Chiba , Toshihiro Tanaka , Takeshi Tomifuji
发明人： Keisuke Chiba , Toshihiro Tanaka , Takeshi Tomifuji
IPC分类号： C11D1/80 , C09K3/00
CPC分类号： C11D1/29 , A61K8/86 , A61Q5/02 , A61Q19/10 , B01F17/0057 , C07C303/24 , C07C305/10
摘要： The invention relates to a surfactant composition containing an alkyl ether sulfate represented by the following formula (1): RO—(PO)m(EO)nSO3M (1) wherein R represents a linear alkyl group having 8 to 24 carbon atoms, PO and EO represent a propyleneoxy group and an ethyleneoxy group, respectively, m and n denote the average numbers of added moles of PO and EO, respectively, and are numbers meeting: 0
摘要翻译：本发明涉及含有下式（1）表示的烷基醚硫酸盐的表面活性剂组合物：RO-（PO）m（EO）nSO3M（1）其中R表示碳原子数为8〜24的直链烷基，PO和 EO分别表示丙烯氧基和亚乙基氧基，m和n分别表示PO和EO的平均加成摩尔数，分别满足：0

47. 发明申请

US20100056821A1 PROCESS FOR PRODUCTION OF ALKYLENE OXIDE ADDUCTS 有权
标题翻译：生产烷基氧化铝助剂的方法
公开(公告)号：US20100056821A1
公开(公告)日：2010-03-04
申请号：US12514465
申请日：2007-10-29
申请人： Yasuki Ohtawa , Toshihiro Tanaka , Kaoru Ohmae
发明人： Yasuki Ohtawa , Toshihiro Tanaka , Kaoru Ohmae
IPC分类号： C07C69/00
CPC分类号： C07C41/03 , C07C41/44 , C07C43/13
摘要： The present invention relates to a process for producing an alkyleneoxide adduct, including the steps of reacting an aliphatic alcohol containing a hydrocarbon group having 6 to 22 carbon atoms with an alkyleneoxide in the presence of a catalyst to obtain a reaction product containing an alkyleneoxide adduct; and subjecting the reaction product successively to acid treatment and reduction treatment, and an alkyleneoxide adduct having a carbonyl value of 5 μmol/g or less. The alkyleneoxide adduct is useful as a raw material of various anionic surfactants, and the anionic surfactants derived from the alkyleneoxide adduct are free from undesirable coloration.
摘要翻译：本发明涉及一种生产环氧烷烃加合物的方法，包括在催化剂存在下使含有6-22个碳原子的烃基的脂族醇与环氧烷反应的步骤，得到含有环氧烷烃加成物的反应产物; 并对反应产物进行酸处理和还原处理，以及羰基值为5μmol/ g以下的环氧烷烃加合物。环氧烷烃加合物可用作各种阴离子表面活性剂的原料，衍生自环氧烷烃加合物的阴离子表面活性剂没有不希望的着色。

48. 发明授权

US07610434B2 File recording apparatus 有权
标题翻译：文件记录装置
公开(公告)号：US07610434B2
公开(公告)日：2009-10-27
申请号：US10578270
申请日：2004-10-07
申请人： Hiroshi Saito , Toshihiro Tanaka
发明人： Hiroshi Saito , Toshihiro Tanaka
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F3/0656 , G06F3/0613 , G06F3/0679
摘要： To effectively record files onto a semiconductor memory, a file recording apparatus has a plurality of file buffers provided for the respective files. Data requested to be written is accumulated in a corresponding file buffer. A judgment is made as to whether data having been accumulated reaches the size of one block, which is a unit of erasing the semiconductor memory. If it is judged that data accumulated in one of the file buffers or in the plurality of file buffers in total has reached the block size, the accumulated data is written into a free block of the semiconductor memory.
摘要翻译：为了有效地将文件记录到半导体存储器上，文件记录装置具有为各个文件提供的多个文件缓冲器。请求写入的数据累积在相应的文件缓冲区中。判断已累积的数据是否达到擦除半导体存储器的单位的一个块的大小。如果判断在一个文件缓冲器中或在多个文件缓冲器中的总共累积的数据已经达到块大小，则将累加的数据写入半导体存储器的空闲块。

49. 发明申请

US20090263036A1 ENCODING DEVICE AND ENCODING METHOD 有权
标题翻译：编码设备和编码方法
公开(公告)号：US20090263036A1
公开(公告)日：2009-10-22
申请号：US12439021
申请日：2007-10-16
申请人： Toshihiro Tanaka
发明人： Toshihiro Tanaka
IPC分类号： G06K9/00 , H03M7/00
CPC分类号： H03M7/4006 , H04N19/124 , H04N19/14 , H04N19/15 , H04N19/194 , H04N19/61 , H04N19/91
摘要： An encoding device 100 includes a quantization parameter generating circuit 111 that generates a provisional quantization parameter, a quantizing circuit 121 that generates quantized data by quantizing a signal to be quantized on the basis of the provisional quantization parameter, a binarizing circuit 131 that binarizes the quantized data to output binary symbol data, an arithmetic coding circuit 141 that generates coded data by arithmetic-coding the binary symbol data, a quantization parameter calculating circuit 112 that generates a suitable quantization parameter on the basis of a symbol amount of the binary symbol data, a code amount of the coded data, an upper limit of the symbol amount, and an target code amount, a quantizing circuit 122 that quantizes the signal to be quantized on the basis of the suitable quantization parameter.
摘要翻译：编码装置100包括产生临时量化参数的量化参数生成电路111，通过基于临时量化参数对要量化的信号进行量化而生成量化数据的量化电路121，二值化电路131，用于输出二进制符号数据的数据，通过对二进制符号数据进行算术编码生成编码数据的算术编码电路141，量化参数计算电路112，其基于二进制符号数据的符号量生成适当的量化参数，编码数据的代码量，符号量的上限和目标代码量，量化电路122，其根据适当的量化参数对待量化的信号进行量化。

50. 发明申请

US20090213649A1 Semiconductor processing device and IC card 有权
标题翻译：半导体处理装置和IC卡
公开(公告)号：US20090213649A1
公开(公告)日：2009-08-27
申请号：US10521553
申请日：2002-08-29
申请人： Masatoshi Takahashi , Takanori Yamazoe , Kozo Katayama , Toshihiro Tanaka , Yutaka Shinagawa , Hiroshi Watase , Takeo Kanai , Nobutaka Nagasaki
发明人： Masatoshi Takahashi , Takanori Yamazoe , Kozo Katayama , Toshihiro Tanaka , Yutaka Shinagawa , Hiroshi Watase , Takeo Kanai , Nobutaka Nagasaki
IPC分类号： G11C11/34 , G11C16/04 , G11C5/14 , G06F12/14
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/40975 , G07F7/084 , G11C11/005 , G11C16/0425 , G11C16/0433 , G11C16/16
摘要： A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately. Therefore, the stored information can efficiently be erased before the execution of a processing of writing the program, and the stored information can be erased corresponding to the data length of a necessary processing unit in the write of the encryption key to be utilized in the calculation processing of the CPU.
摘要翻译：根据本发明的半导体处理装置包括用于擦除第一数据长度单元上存储的信息的第一非易失性存储器（21），用于擦除第二数据长度单元上存储的信息的第二非易失性存储器（22），以及中央处理单元（2），能够从/向外部输入/输出加密数据。第一非易失性存储器用于存储要用于加密数据的加密密钥。第二非易失性存储器用于存储要由中央处理单元处理的程序。用于存储程序和用于存储加密密钥的非易失性存储器彼此分离，并且存储在非易失性存储器中的信息的擦除单元的数据长度被分开地定义。因此，在执行写入程序的处理之前可以有效地擦除存储的信息，并且可以根据在计算中要使用的加密密钥的写入中的必要处理单元的数据长度来擦除存储的信息处理CPU。

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