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41. 发明授权

US08227278B2 Methods for manufacturing thin film transistor and display device 有权
标题翻译：制造薄膜晶体管和显示装置的方法
公开(公告)号：US08227278B2
公开(公告)日：2012-07-24
申请号：US12545276
申请日：2009-08-21
申请人： Shinya Sasagawa , Akihiro Ishizuka , Shigeki Komori
发明人： Shinya Sasagawa , Akihiro Ishizuka , Shigeki Komori
IPC分类号： H01L33/00 , H01L21/336
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/1255 , H01L29/04 , H01L29/41733 , H01L29/66765 , H01L29/78696
摘要： The present invention provides a method for manufacturing a thin film transistor with small leakage current and high switching characteristics. In a method for manufacturing a thin film transistor, a back channel portion is formed in the thin film transistor by conducting etching using a resist mask, the resist mask is removed by removal or the like, and a superficial part of the back channel portion is further etched. Through the steps, components of chemical solution used for the removal, residues of the resist mask, and the like which exist at the superficial part of the back channel portion can be removed and leakage current can be reduced. The further etching step of the back channel portion is preferably conducted by dry etching using an N2 gas or a CF4 gas with bias not applied.
摘要翻译：本发明提供一种制造漏电流小，开关特性高的薄膜晶体管的制造方法。在制造薄膜晶体管的方法中，通过使用抗蚀剂掩模进行蚀刻，在薄膜晶体管中形成背沟道部分，通过去除等除去抗蚀剂掩模，并且背沟道部分的表面部分是进一步刻蚀。通过这些步骤，可以去除存在于背部通道部分的表面部分的用于去除的化学溶液的组分，抗蚀剂掩模的残留物等，并且可以减少泄漏电流。后通道部分的进一步蚀刻步骤优选通过使用N 2气体或没有施加偏压的CF 4气体进行干蚀刻来进行。

42. 发明授权

US08236635B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08236635B2
公开(公告)日：2012-08-07
申请号：US12582074
申请日：2009-10-20
申请人： Hideomi Suzawa , Shinya Sasagawa , Taiga Muraoka
发明人： Hideomi Suzawa , Shinya Sasagawa , Taiga Muraoka
IPC分类号： H01L21/00 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L21/20
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/1225 , H01L29/7869
摘要： In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. The etching step is performed by dry etching in which an etching gas is used.
摘要翻译：在制造包括通道蚀刻反交错薄膜晶体管的半导体器件的方法中，使用使用作为曝光的多色调掩模形成的掩模层来蚀刻氧化物半导体膜和导电膜光透过该掩模以具有多个强度。蚀刻步骤通过使用蚀刻气体的干蚀刻进行。

43. 发明授权

US08207025B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08207025B2
公开(公告)日：2012-06-26
申请号：US13078020
申请日：2011-04-01
申请人： Hideomi Suzawa , Shinya Sasagawa
发明人： Hideomi Suzawa , Shinya Sasagawa
IPC分类号： H01L21/336
CPC分类号： H01L29/78636 , G11C16/0433 , H01L27/0688 , H01L27/11521 , H01L27/11551 , H01L27/1156 , H01L27/1214 , H01L27/1225 , H01L27/1288 , H01L29/66969 , H01L29/7869
摘要： In an embodiment, an insulating film is formed over a flat surface; a mask is formed over the insulating film; a slimming process is performed on the mask; an etching process is performed on the insulating film using the mask; a conductive film covering the insulating film is formed; a polishing process is performed on the conductive film and the insulating film, so that the conductive film and the insulating film have equal thicknesses; the conductive film is etched, so that a source electrode and a drain electrode which are thinner than the conductive film are formed; an oxide semiconductor film is formed in contact with the insulating film, the source electrode, and the drain electrode; a gate insulating film covering the oxide semiconductor film is formed; and a gate electrode is formed in a region which is over the gate insulating film and overlaps with the insulating film.
摘要翻译：在一个实施例中，在平坦表面上形成绝缘膜; 在绝缘膜上形成掩模; 在面罩上进行减肥过程; 使用掩模对绝缘膜进行蚀刻处理; 形成覆盖绝缘膜的导电膜; 对导电膜和绝缘膜进行抛光处理，使得导电膜和绝缘膜具有相等的厚度; 蚀刻导电膜，形成比导电膜薄的源电极和漏电极; 形成与绝缘膜，源电极和漏电极接触的氧化物半导体膜; 形成覆盖氧化物半导体膜的栅极绝缘膜; 并且栅电极形成在栅极绝缘膜上并与绝缘膜重叠的区域中。

44. 发明授权

US07989351B2 Method for manufacturing a wiring over a substrate 有权
标题翻译：在基板上制造布线的方法
公开(公告)号：US07989351B2
公开(公告)日：2011-08-02
申请号：US12431170
申请日：2009-04-28
申请人： Shinya Sasagawa , Satoru Okamoto , Shigeharu Monoe
发明人： Shinya Sasagawa , Satoru Okamoto , Shigeharu Monoe
IPC分类号： H01L21/302
CPC分类号： H01L27/3276 , G02F2001/13629 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L51/0021 , H01L51/0023 , H01L51/5281 , H01L2924/0002 , H05K3/06 , H05K2203/0315 , H05K2203/0346 , H05K2203/095 , H05K2203/1476 , H01L2924/00
摘要： A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression between wirings and a method for manufacturing the wiring is also disclosed. Further, a wiring over a substrate capable of preventing cracks in the insulating layer due to stress at the edge of a wiring or particles and a method for manufacturing the wiring is also disclosed. According to the present invention, a method for manufacturing a wiring over a substrate is provided that comprises the steps of: forming a first conductive layer over an insulating surface; forming a first mask pattern over the first conductive layer; forming a second mask pattern by etching the first mask pattern under a first condition, simultaneously, forming a second conductive layer having a side having an angle of inclination cross-sectionally by etching the first conductive layer; and forming a third conductive layer and a third mask pattern by etching the second conductive layer and the second mask pattern under a second condition; wherein a selective ratio under the first condition of the first conductive layer to the first mask pattern is in a range of 0.25 to 4, and a selective ratio under the second condition of the second conductive layer to the second mask pattern is larger than that under the first condition.
摘要翻译：公开了一种能够减少布线之间的颗粒的基板上的布线和用于制造布线的方法。还公开了一种能够防止布线之间的大的差异和配线间的凹陷之间的布线之间的短路的布线和布线的制造方法。此外，还公开了能够防止由于布线或颗粒的边缘处的应力导致的绝缘层中的裂纹的基板上的布线以及布线的制造方法。根据本发明，提供了一种用于在衬底上制造布线的方法，包括以下步骤：在绝缘表面上形成第一导电层; 在所述第一导电层上形成第一掩模图案; 通过在第一条件下蚀刻第一掩模图案形成第二掩模图案，同时通过蚀刻第一导电层形成具有横截面为倾斜角的一侧的第二导电层; 以及通过在第二条件下蚀刻所述第二导电层和所述第二掩模图案来形成第三导电层和第三掩模图案; 其中在第一导电层与第一掩模图案的第一条件下的选择比在0.25至4的范围内，并且在第二导电层与第二掩模图案的第二条件下的选择比大于第一个条件。

45. 发明授权

US07968884B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07968884B2
公开(公告)日：2011-06-28
申请号：US11945739
申请日：2007-11-27
申请人： Shunpei Yamazaki , Kazuko Ikeda , Shinya Sasagawa , Hideomi Suzawa
发明人： Shunpei Yamazaki , Kazuko Ikeda , Shinya Sasagawa , Hideomi Suzawa
IPC分类号： H01L29/10 , H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L29/4908 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78609
摘要： A semiconductor device manufactured utilizing an SOI substrate, in which defects due to an end portion of an island-shaped silicon layer are prevented and the reliability is improved, and a manufacturing method thereof. The following are included: an SOI substrate in which an insulating layer and an island-shaped silicon layer are stacked in order over a support substrate; a gate insulating layer provided over one surface and a side surface of the island-shaped silicon layer; and a gate electrode which is provided over the island-shaped silicon layer with the gate insulating layer interposed therebetween. The gate insulating layer is formed such that the dielectric constant in the region which is in contact with the side surface of the island-shaped silicon layer is lower than that over the one surface of the island-shaped silicon layer.
摘要翻译：利用SOI衬底制造的半导体器件及其制造方法，其中防止了由岛状硅层的端部引起的缺陷并提高了可靠性。包括以下：SOI基板，其中绝缘层和岛状硅层依次层叠在支撑基板上; 设置在岛状硅层的一个表面和侧面上的栅极绝缘层; 以及栅极电极，其设置在岛状硅层上，栅极绝缘层插入其间。栅极绝缘层形成为与岛状硅层的侧面接触的区域的介电常数低于岛状硅层的一个表面的介电常数。

46. 发明授权

US07915075B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07915075B2
公开(公告)日：2011-03-29
申请号：US12580512
申请日：2009-10-16
申请人： Hideomi Suzawa , Shinya Sasagawa , Taiga Muraoka
发明人： Hideomi Suzawa , Shinya Sasagawa , Taiga Muraoka
IPC分类号： H01L21/00 , H01L21/16
CPC分类号： H01L27/127 , G02F1/134309 , G02F1/136227 , G02F1/167 , G09F21/04 , G09G3/3648 , G09G3/3677 , G09G2300/0408 , G09G2300/0809 , G09G2310/0251 , G09G2310/0286 , G09G2310/08 , G11C19/28 , H01L21/465 , H01L27/1225 , H01L27/124 , H01L27/3262 , H01L29/66969 , H01L29/7869 , H01L29/78696
摘要： An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.
摘要翻译：本发明的目的是建立一种其中使用氧化物半导体的半导体器件的制造中的加工技术。在基板上形成栅电极，在栅电极上形成栅极绝缘层，在栅极绝缘层上形成氧化物半导体层，通过湿蚀刻加工氧化物半导体层，形成岛状氧化物半导体层形成导电层以覆盖岛状氧化物半导体层，通过干蚀刻处理导电层以形成源电极，并且通过干蚀刻除去漏电极和岛状氧化物半导体层的一部分，在岛状氧化物半导体层中形成凹部。

47. 发明授权

US07709368B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07709368B2
公开(公告)日：2010-05-04
申请号：US12046881
申请日：2008-03-12
申请人： Shinya Sasagawa
发明人： Shinya Sasagawa
IPC分类号： H01L21/4763
CPC分类号： H01L21/76804 , H01L23/485 , H01L27/124 , H01L29/41733 , H01L2924/0002 , H01L2924/00
摘要： A method for easily manufacturing a semiconductor device in which variation in thickness or disconnection of a source electrode or a drain electrode is prevented is proposed A semiconductor device includes a semiconductor layer formed over an insulating substrate; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; an opening which reaches the semiconductor layer and is formed at least in the first insulating layer and the second insulating layer; and a step portion formed at a side surface of the second insulating layer in the opening.
摘要翻译：提出一种容易制造其中防止源电极或漏电极的厚度变化或断开的半导体器件的方法。一种半导体器件包括形成在绝缘基板上的半导体层; 形成在所述半导体层上的第一绝缘层; 形成在所述第一绝缘层上的栅电极; 形成在所述栅电极上的第二绝缘层; 至少形成在所述第一绝缘层和所述第二绝缘层中的至少形成在所述半导体层上的开口部; 以及形成在所述开口中的所述第二绝缘层的侧表面处的台阶部。

48. 发明申请

US20100102315A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100102315A1
公开(公告)日：2010-04-29
申请号：US12582082
申请日：2009-10-20
申请人： Hideomi Suzawa , Shinya Sasagawa , Taiga Muraoka , Shunichi Ito , Miyuki Hosoba
发明人： Hideomi Suzawa , Shinya Sasagawa , Taiga Muraoka , Shunichi Ito , Miyuki Hosoba
IPC分类号： H01L29/786
CPC分类号： H01L29/66969 , H01L27/1225 , H01L27/1288 , H01L29/66742 , H01L29/78621 , H01L29/7869
摘要： An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used.
摘要翻译：目的是以低成本，高生产率制造包括氧化物半导体的半导体器件，使得通过减少曝光掩模的数量来简化光刻工艺。在制造包括通道蚀刻反交错薄膜晶体管的半导体器件的方法中，使用使用作为曝光的多色调掩模形成的掩模层来蚀刻氧化物半导体膜和导电膜光透过该掩模以具有多个强度。在蚀刻步骤中，通过使用蚀刻剂的湿式蚀刻进行第一蚀刻步骤，并且通过使用蚀刻气体的干法蚀刻进行第二蚀刻步骤。

49. 发明授权

US07622785B2 Photoelectric conversion element and manufacturing method of photoelectric conversion element 有权
标题翻译：光电转换元件及光电转换元件的制造方法
公开(公告)号：US07622785B2
公开(公告)日：2009-11-24
申请号：US11737477
申请日：2007-04-19
申请人： Shinya Sasagawa , Shinya Hasegawa , Hidekazu Takahashi , Tatsuya Arao
发明人： Shinya Sasagawa , Shinya Hasegawa , Hidekazu Takahashi , Tatsuya Arao
IPC分类号： H01L31/075 , H01L31/18
CPC分类号： H01L31/035281 , H01L21/32136 , H01L21/32137 , H01L27/14643 , Y02E10/50
摘要： An object is to provide a photoelectric conversion element having a side surface with different taper angles by conducting etching of a photoelectric conversion layer step-by-step. A pin photodiode has a high response speed compared with a pn photodiode but has a disadvantage of large dark current. One cause of the dark current is considered to be conduction through an etching residue which is generated in etching and deposited on a side surface of the photoelectric conversion layer. Leakage current of the photoelectric conversion element is reduced by forming a structure in which a side surface has two different tapered shapes, which conventionally has a uniform surface, so that the photoelectric conversion layer has a side surface of a p-layer and a side surface of an n-layer, which are not in the same plane.
摘要翻译：本发明的目的是提供一种具有不同锥角的侧面的光电转换元件，该光电转换元件逐步进行光电转换层的蚀刻。与pn光电二极管相比，pin光电二极管具有高响应速度，但是具有大的暗电流的缺点。认为暗电流的一个原因是通过在蚀刻中产生并沉积在光电转换层的侧表面上的蚀刻残余物导电。光电转换元件的泄漏电流通过形成侧表面具有两个不同的锥形形状的结构而降低，通常具有均匀的表面，使得光电转换层具有p层的侧表面和侧表面的n层，它们不在同一平面。

50. 发明授权

US07579270B2 Method for manufacturing a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07579270B2
公开(公告)日：2009-08-25
申请号：US11600835
申请日：2006-11-17
申请人： Tomohiko Sato , Shigeharu Monoe , Shinya Sasagawa
发明人： Tomohiko Sato , Shigeharu Monoe , Shinya Sasagawa
IPC分类号： H01L21/4763
CPC分类号： H01L21/31116 , H01L21/76802 , H01L21/76804 , H01L21/76819 , H01L27/12 , H01L27/1248 , H01L29/41733
摘要： It is an object of the present invention to provide a method for manufacturing a highly reliable semiconductor device with preferable yield. In the invention, two-step etching is performed when selectively removing an interlayer insulating film with at least two layers constituting a semiconductor device, and forming an opening. One feature of the invention is that at least either one of a first gas (a first etching gas) and a second gas (a second etching gas) used at the time of the two-step etching is added with an inert gas.
摘要翻译：本发明的目的是提供一种制造高可靠性半导体器件的方法，该方法具有优异的收率。在本发明中，当选择性地去除构成半导体器件的至少两层的层间绝缘膜并形成开口时，进行两步蚀刻。本发明的一个特征是在两步蚀刻时使用的第一气体（第一蚀刻气体）和第二气体（第二蚀刻气体）中的至少任一种加入惰性气体。

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