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41. 发明授权

US07940562B2 Non-volatile semiconductor memory device having non-selected word lines adjacent to selected word lines being charged at different timing for program disturb control 有权
标题翻译：具有与所选字线相邻的未选字线的非易失性半导体存储器件在不同的定时被充电用于程序干扰控制
公开(公告)号：US07940562B2
公开(公告)日：2011-05-10
申请号：US12689786
申请日：2010-01-19
申请人： Hiroshi Nakamura , Tomoharu Tanaka
发明人： Hiroshi Nakamura , Tomoharu Tanaka
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/30
摘要： A non-volatile semiconductor memory device includes a memory cell array of data-rewritable non-volatile memory cells or memory cell units containing the memory cells, and a plurality of word lines each commonly connected to the memory cells on the same row in the memory cell array. In write pulse applying during data writing, a high voltage for writing is applied to a selected word line, and an intermediate voltage for writing is applied to at least two of non-selected word lines. The beginning of charging a first word line located between the selected word line and a source line to a first intermediate voltage for writing is followed by the beginning of charging a second word line located between the selected word line and a bit line contact to a second intermediate voltage for writing.
摘要翻译：非挥发性半导体存储器件包括数据可重写非易失性存储器单元的存储单元阵列或包含存储单元的存储单元单元，以及多个字线，每个字线共同连接到存储器中相同行上的存储器单元单元格阵列。在数据写入期间的写入脉冲施加中，写入用的高电压被施加到所选择的字线，并且用于写入的中间电压被施加到至少两个未选择的字线。将位于所选择的字线和源极线之间的第一字线充电到用于写入的第一中间电压的开始之后，将位于所选择的字线和位线接触之间的第二字线开始充电到第二写入中间电压。

42. 发明申请

US20080062764A1 Nonvolatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20080062764A1
公开(公告)日：2008-03-13
申请号：US11929210
申请日：2007-10-30
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C2211/5621
摘要： A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.
摘要翻译： NAND单元单元包括串联连接的存储单元。对所有存储单元进行擦除操作。然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极记忆细胞因此数据被编程到所选择的存储单元中。根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

43. 发明授权

US06972996B2 Pattern layout of transfer transistors employed in row decoder 失效
公开(公告)号：US06972996B2
公开(公告)日：2005-12-06
申请号：US10922950
申请日：2004-08-23
申请人： Koji Hosono , Hiroshi Nakamura , Kenichi Imamiya , Tomoharu Tanaka
发明人： Koji Hosono , Hiroshi Nakamura , Kenichi Imamiya , Tomoharu Tanaka
IPC分类号： H01L21/8247 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/08 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/06
CPC分类号： G11C8/10 , G11C8/08 , G11C16/0483 , G11C16/08
摘要： A semiconductor device comprises a memory cell array and a word-line select circuit. The memory cell array includes a plurality of memory cells arranged in rows and columns. The memory cell array includes a plurality of blocks in each one of which the memory cells are arranged. The word-line select circuit includes transfer transistors arranged in row and column directions, and is configured to transfer a plurality of different voltages to word lines through current paths of the transfer transistors and select memory cells of at least one row of said plurality of blocks. The transfer transistors include a first group, which transfers the lowest voltage of voltages applied to the word lines in a writing operation and a second group, which is arranged not to be adjacent to the first group and transfers the highest voltage of voltages applied to the word lines in a writing operation.

44. 发明授权

US06940752B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US06940752B2
公开(公告)日：2005-09-06
申请号：US10920161
申请日：2004-08-18
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C7/00 , G11C11/56 , G11C16/34 , G11C16/04
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C2211/5621
摘要： A NAND cell unit includes a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

45. 发明授权

US06859401B2 Fail number detecting circuit of flash memory 有权
标题翻译：闪存的故障号检测电路
公开(公告)号：US06859401B2
公开(公告)日：2005-02-22
申请号：US10674404
申请日：2003-10-01
申请人： Koji Hosono , Tamio Ikehashi , Tomoharu Tanaka , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi
发明人： Koji Hosono , Tamio Ikehashi , Tomoharu Tanaka , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/34 , G11C29/04 , G11C29/12
CPC分类号： G11C16/3445 , G11C16/3436 , G11C16/3459
摘要： A semiconductor device includes a memory cell array, latch circuits, first to third circuits and a current control circuit. The memory cell array includes NAND cells arranged therein. The latch circuits temporarily hold data read out from the memory cell array. The first circuit generates a first current varying in proportion to “1” or “0” of binary logic data of one end of the plurality of latch circuits. The second circuit generates a second current which is preset. The third circuit compares the first current with the second current. The value of “1” or “0” of binary logic data of the one end of the plurality of latch circuits is detected based on a result of the comparison between the first current and the second current.
摘要翻译：半导体器件包括存储单元阵列，锁存电路，第一至第三电路和电流控制电路。存储单元阵列包括其中布置的NAND单元。锁存电路暂时保存从存储单元阵列读出的数据。第一电路产生与多个锁存电路的一端的二进制逻辑数据的“1”或“0”成比例变化的第一电流。第二电路产生预置的第二电流。第三电路将第一电流与第二电流进行比较。基于第一电流和第二电流之间的比较结果，检测多个锁存电路一端的二进制逻辑数据的“1”或“0”值。

46. 发明申请

US20050018462A1 Pattern layout of transfer transistors employed in row decoder 失效
标题翻译：在行解码器中使用的转移晶体管的图案布局
公开(公告)号：US20050018462A1
公开(公告)日：2005-01-27
申请号：US10922950
申请日：2004-08-23
申请人： Koji Hosono , Hiroshi Nakamura , Kenichi Imamiya , Tomoharu Tanaka
发明人： Koji Hosono , Hiroshi Nakamura , Kenichi Imamiya , Tomoharu Tanaka
IPC分类号： H01L21/8247 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/08 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C19/08
CPC分类号： G11C8/10 , G11C8/08 , G11C16/0483 , G11C16/08
摘要： A semiconductor device comprises a memory cell array and a word-line select circuit. The memory cell array includes a plurality of memory cells arranged in rows and columns. The memory cell array includes a plurality of blocks in each one of which the memory cells are arranged. The word-line select circuit includes transfer transistors arranged in row and column directions, and is configured to transfer a plurality of different voltages to word lines through current paths of the transfer transistors and select memory cells of at least one row of said plurality of blocks. The transfer transistors include a first group, which transfers the lowest voltage of voltages applied to the word lines in a writing operation and a second group, which is arranged not to be adjacent to the first group and transfers the highest voltage of voltages applied to the word lines in a writing operation.
摘要翻译：半导体器件包括存储单元阵列和字线选择电路。存储单元阵列包括以行和列排列的多个存储单元。存储单元阵列包括其中每个存储单元被布置的多个块。字线选择电路包括以列和列方向布置的传输晶体管，并且被配置为通过传输晶体管的电流路径将多个不同的电压传送到字线，并且选择所述多个块的至少一行的存储单元。转移晶体管包括第一组，其在写入操作中传送施加到字线的最低电压电压，第二组被布置为不与第一组相邻，并且传送施加到第一组的最高电压电压写字操作中的字线。

47. 发明授权

US06657896B2 Fail number detecting circuit of flash memory 有权
标题翻译：闪存的故障号检测电路
公开(公告)号：US06657896B2
公开(公告)日：2003-12-02
申请号：US10315050
申请日：2002-12-10
申请人： Koji Hosono , Tamio Ikehashi , Tomoharu Tanaka , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi
发明人： Koji Hosono , Tamio Ikehashi , Tomoharu Tanaka , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi
IPC分类号： G11C1606
CPC分类号： G11C16/3445 , G11C16/3436 , G11C16/3459
摘要： A semiconductor memory device includes a memory cell array, latch circuits, first to third circuits and a current control circuit. The memory cell array includes electrically rewritable nonvolatile memory cells arranged therein. The latch circuits temporarily hold data read out from the memory cell array. The first circuit generates a first current which varies in proportion to “1” or “0” of binary logical data of one end of the latch circuits. The second circuit generates a predetermined second current. The current control circuit is connected to the first and second circuits, and configured to determined absolute values of the first and second currents. The third circuit is configured to compare the first and second currents. The number of binary logical data of “1” or “0” of one end of the latch circuits is detected based on the result of comparison between the first and second currents.
摘要翻译：半导体存储器件包括存储单元阵列，锁存电路，第一至第三电路和电流控制电路。存储单元阵列包括布置在其中的电可重写非易失性存储单元。锁存电路暂时保存从存储单元阵列读出的数据。第一电路产生与锁存电路的一端的二进制逻辑数据的“1”或“0”成比例变化的第一电流。第二电路产生预定的第二电流。电流控制电路连接到第一和第二电路，并被配置为确定第一和第二电流的绝对值。第三电路被配置为比较第一和第二电流。基于第一和第二电流之间的比较结果来检测锁存电路的一端的“1”或“0”的二进制逻辑数据的数量。

48. 发明授权

US06549464B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US06549464B2
公开(公告)日：2003-04-15
申请号：US10187285
申请日：2002-07-02
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C2211/5621
摘要： A NAND cell unit comprising a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

49. 发明授权

US06434055B1 Nonvolatile semiconductor memory device 有权
公开(公告)号：US06434055B1
公开(公告)日：2002-08-13
申请号：US09767152
申请日：2001-01-23
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C1604
摘要： A NAND cell unit comprising a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

50. 发明授权

US5818791A Non-volatile semiconductor memory device and memory system using the same 失效
公开(公告)号：US5818791A
公开(公告)日：1998-10-06
申请号：US826152
申请日：1997-03-27
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G06F11/10 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/34 , G11C29/00 , G11C29/34 , G11C29/52 , G11C13/00
CPC分类号： G11C29/785 , G06F11/1008 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3454 , G11C29/34 , G11C29/52 , G06F11/1068 , G06F2201/81 , G06F2212/2022
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

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