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41. 发明授权

US08709890B2 Method and structure for forming ETSOI capacitors, diodes, resistors and back gate contacts 有权
标题翻译：用于形成ETSOI电容器，二极管，电阻器和背栅极触点的方法和结构
公开(公告)号：US08709890B2
公开(公告)日：2014-04-29
申请号：US13316641
申请日：2011-12-12
申请人： Kangguo Cheng , Thomas N. Adam , Ali Khakifirooz , Alexander Reznicek
发明人： Kangguo Cheng , Thomas N. Adam , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/8244
CPC分类号： H01L21/84 , H01L27/0629 , H01L27/1203 , H01L27/1207 , H01L27/13 , H01L28/10 , H01L29/8611 , H01L29/94
摘要： An ETSOI transistor and a combination of capacitors, junction diodes, bank end contacts and resistors are respectively formed in a transistor and capacitor region thereof by etching through an ETSOI and BOX layers in a replacement gate HK/MG flow. The capacitor and other devices formation are compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor, and devices. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.
摘要翻译：通过在替换栅极HK / MG流中蚀刻ETSOI和BOX层，在其晶体管和电容器区域中分别形成ETSOI晶体管以及电容器，结二极管，堤端触点和电阻器的组合。电容器和其他器件形成与ETSOI替代栅极CMOS流相兼容。低电阻电容器电极可以获得高质量的电容器和器件。虚拟栅极图案化期间缺乏形貌通过光刻结合并伴随着适当的蚀刻来实现。

42. 发明申请

US20140061820A1 BULK FINFET WITH CONTROLLED FIN HEIGHT AND HIGH-K LINER 有权
标题翻译：具有控制高度和高K内衬的大容量FINFET
公开(公告)号：US20140061820A1
公开(公告)日：2014-03-06
申请号：US13604658
申请日：2012-09-06
申请人： Alexander Reznicek , Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz
发明人： Alexander Reznicek , Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz
IPC分类号： H01L21/336 , H01L27/088
CPC分类号： H01L29/785 , H01L21/823821 , H01L27/0924 , H01L29/0684 , H01L29/1054 , H01L29/66795
摘要： A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second dielectric layer is a high-k dielectric. Openings are formed through the material stack to expose a surface of the semiconductor substrate. A semiconductor material is formed in the openings through the material stack. The first dielectric layer is removed selectively to the second dielectric layer and the semiconductor material. A gate structure is formed on a channel portion of the semiconductor material. In some embodiments, the method may provide a plurality of finFET or trigate semiconductor device in which the fin structures of those devices have substantially the same height.
摘要翻译：一种形成半导体器件的方法，包括在半导体衬底上形成材料堆叠，所述材料堆叠包括在所述衬底上的第一介电层，所述第一电介质层上的第二电介质层和所述第二电介质层上的第三电介质层，其中所述第二电介质层是高k电介质。通过材料堆叠形成开口以暴露半导体衬底的表面。通过材料堆叠在开口中形成半导体材料。第一电介质层被选择性地去除到第二电介质层和半导体材料。栅极结构形成在半导体材料的沟道部分上。在一些实施例中，该方法可以提供多个finFET或者触发半导体器件，其中这些器件的鳍结构具有基本上相同的高度。

43. 发明申请

US20140042547A1 HIGH DENSITY BULK FIN CAPACITOR 有权
标题翻译：高密度散热片电容器
公开(公告)号：US20140042547A1
公开(公告)日：2014-02-13
申请号：US13584176
申请日：2012-08-13
申请人： Ali Khakifirooz , Thomas N. Adam , Kangguo Cheng , Alexander Reznicek
发明人： Ali Khakifirooz , Thomas N. Adam , Kangguo Cheng , Alexander Reznicek
IPC分类号： H01L27/088 , G06F17/50 , H01L21/02
CPC分类号： H01L28/92 , H01L27/0805 , H01L29/785
摘要： A high density bulk fin capacitor is disclosed. Fin capacitors are formed near finFETs by further etching the fin capacitors to provide more surface area, resulting in increased capacitance density. Embodiments of the present invention include depletion-mode varactors and inversion-mode varactors.
摘要翻译：公开了一种高密度散装散热片电容器。通过进一步蚀刻散热片电容器以提供更多的表面积，从而在finFET附近形成翅片电容器，从而增加电容密度。本发明的实施例包括耗尽型变容二极管和反模式变容二极管。

44. 发明授权

US08592916B2 Selectively raised source/drain transistor 有权
标题翻译：选择性地升高源极/漏极晶体管
公开(公告)号：US08592916B2
公开(公告)日：2013-11-26
申请号：US13424787
申请日：2012-03-20
申请人： Ali Khakifirooz , Thomas N. Adam , Kangguo Cheng , Alexander Reznicek
发明人： Ali Khakifirooz , Thomas N. Adam , Kangguo Cheng , Alexander Reznicek
IPC分类号： H01L21/02
CPC分类号： H01L27/088 , H01L21/823418 , H01L21/823431 , H01L21/823475 , H01L29/41791 , H01L29/66628 , H01L29/7834
摘要： A lower raised source/drain region is formed on a planar source/drain region of a planar field effect transistor or a surface of a portion of semiconductor fin adjoining a channel region of a fin field effect transistor. At least one contact-level dielectric material layer is formed and planarized, and a contact via hole extending to the lower raised source/drain region is formed in the at least one contact-level dielectric material layer. An upper raised source/drain region is formed on a top surface of the lower raised source/drain region. A metal semiconductor alloy portion and a contact via structure are formed within the contact via hole. Formation of the upper raised source/drain region is limited to a bottom portion of the contact via hole, thereby preventing formation of, and increase of parasitic capacitance by, any additional raised structure in source/drain regions that are not contacted.
摘要翻译：在平面场效应晶体管的平面源极/漏极区域或与鳍状场效应晶体管的沟道区域相邻的半导体鳍片的一部分的表面上形成下部凸起的源极/漏极区域。形成并平坦化至少一个接触层介电材料层，并且在该至少一个接触层电介质材料层中形成延伸到下凸起源/漏区的接触通孔。上凸起的源/漏区形成在下凸起的源/漏区的顶表面上。在接触通孔内形成金属半导体合金部分和接触通孔结构。上部隆起源极/漏极区域的形成被限制在接触通孔的底部，从而通过未被接触的源极/漏极区域中的任何额外的凸起结构来防止寄生电容的形成和增加。

45. 发明申请

US20130270560A1 METHOD FOR FORMING SEMICONDUCTOR DEVICE WITH EPITAXY SOURCE AND DRAIN REGIONS INDEPENDENT OF PATTERNING AND LOADING 审中-公开
标题翻译：用于形成具有外来源和排水区的半导体器件的方法，独立于填充和加载
公开(公告)号：US20130270560A1
公开(公告)日：2013-10-17
申请号：US13448876
申请日：2012-04-17
申请人： Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Yu Zhu , Thomas N. Adam
发明人： Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Yu Zhu , Thomas N. Adam
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor device that includes providing a gate structure on a channel portion of a semiconductor on insulator (SOI) layer of a semiconductor on insulator (SOI) substrate, and forming an amorphous semiconductor layer on at least a source region portion and a drain region portion of the SOI layer. The amorphous semiconductor layer is converted to a crystalline semiconductor material, wherein the crystalline semiconductor material provides a raised source region and a raised drain region of the semiconductor device. The method may be applicable to planar semiconductor devices and finFET semiconductor devices.
摘要翻译：一种制造半导体器件的方法，包括在绝缘体上半导体（SOI）衬底上的半导体绝缘体（SOI）层的沟道部分上提供栅极结构，并且在至少源极区部分上形成非晶半导体层，以及 SOI层的漏极区域部分。将非晶半导体层转换为晶体半导体材料，其中晶体半导体材料提供半导体器件的升高的源极区域和升高的漏极区域。该方法可以应用于平面半导体器件和finFET半导体器件。

46. 发明申请

US20130161693A1 THIN HETEREOSTRUCTURE CHANNEL DEVICE 有权
标题翻译：薄型结构通道设备
公开(公告)号：US20130161693A1
公开(公告)日：2013-06-27
申请号：US13336251
申请日：2011-12-23
申请人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/02057 , H01L21/02532 , H01L21/0262 , H01L21/3065 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/1054
摘要： A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.
摘要翻译：一种制造半导体器件的方法，其包括提供在电介质层顶部具有至少第一半导体层的衬底，其中所述第一半导体层具有小于10nm的第一厚度。在小于675℃的温度下用卤化物基气体蚀刻第一半导体层至小于第一厚度的第二厚度。在第一半导体层的蚀刻表面上外延形成第二半导体层。栅极结构直接形成在第二半导体层上。源极区域和漏极区域形成在栅极结构的相对侧上。

47. 发明申请

US20130099319A1 THIN SEMICONDUCTOR-ON-INSULATOR MOSFET WITH CO-INTEGRATED SILICON, SILICON GERMANIUM AND SILICON DOPED WITH CARBON CHANNELS 有权
标题翻译：具有合并硅，半导体和绝缘体的半导体绝缘体MOSFET，具有碳通道
公开(公告)号：US20130099319A1
公开(公告)日：2013-04-25
申请号：US13607743
申请日：2012-09-09
申请人： Thomas N. Adam , Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/77 , H01L21/823412 , H01L27/092
摘要： A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.
摘要翻译：一种制造半导体器件的方法，其可以从提供半导体衬底开始，所述半导体衬底包括与掩埋电介质层直接接触的包含硅层的第一器件区域，包括与所述掩埋电介质层直接接触的硅锗层的第二器件区域以及掺杂有碳层的硅的第三器件区域。然后可以在半导体衬底的第一器件区域内的硅层上形成至少一个低功率半导体器件。可以在半导体衬底的第二器件区域的硅锗层上形成至少一个p型半导体器件。可以在半导体衬底的第三器件区域的掺杂有碳层的硅上形成至少一个n型半导体器件。

48. 发明申请

US20130099318A1 THIN SEMICONDUCTOR-ON-INSULATOR MOSFET WITH CO-INTEGRATED SILICON, SILICON GERMANIUM AND SILICON DOPED WITH CARBON CHANNELS 审中-公开
公开(公告)号：US20130099318A1
公开(公告)日：2013-04-25
申请号：US13280850
申请日：2011-10-25
申请人： Thomas N. Adam , Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L27/092 , H01L21/20
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/77 , H01L21/823412 , H01L27/092
摘要： A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.

49. 发明申请

US20110263104A1 THIN BODY SEMICONDUCTOR DEVICES 有权
标题翻译：薄体半导体器件
公开(公告)号：US20110263104A1
公开(公告)日：2011-10-27
申请号：US12766859
申请日：2010-04-24
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L21/20
CPC分类号： H01L29/66628 , H01L29/66742 , H01L29/66772 , H01L29/66795 , H01L29/78696
摘要： A method for fabricating an FET device is disclosed. The method includes providing a body over an insulator, with the body having at least one surface adapted to host a device channel. Selecting the body to be Si, Ge, or their alloy mixtures. Choosing the body layer to be less than a critical thickness defined as the thickness where agglomeration may set in during a high temperature processing. Such critical thickness may be about 4 nm for a planar devices, and about 8 nm for a non-planar devices. The method further includes clearing surfaces of oxygen at low temperature, and forming a raised source/drain by selective epitaxy while using the cleared surfaces for seeding. After the clearing of the surfaces of oxygen, and before the selective epitaxy, oxygen exposure of the cleared surfaces is being prevented.
摘要翻译：公开了一种用于制造FET器件的方法。该方法包括在绝缘体上提供主体，其中主体具有适于承载设备通道的至少一个表面。选择身体为Si，Ge或其合金混合物。选择体层小于临界厚度，其临界厚度定义为在高温加工过程中聚集的厚度。这种临界厚度对于平面器件可以是约4nm，对于非平面器件而言约8nm。该方法还包括在低温下清除氧的表面，并且通过选择性外延形成凸起的源极/漏极，同时使用清除的表面进行接种。在氧的表面清除之后，并且在选择性外延之前，防止了清除的表面的氧曝光。

50. 发明申请

US20120210932A1 LOW-TEMPERATURE SELECTIVE EPITAXIAL GROWTH OF SILICON FOR DEVICE INTEGRATION 有权
标题翻译：低温选择性外延生长用于器件集成的硅
公开(公告)号：US20120210932A1
公开(公告)日：2012-08-23
申请号：US13032866
申请日：2011-02-23
申请人： BAHMAN HEKMATSHOAR-TABARI , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
发明人： BAHMAN HEKMATSHOAR-TABARI , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： C30B25/02 , C30B25/10
CPC分类号： C30B25/04 , C30B25/105 , C30B25/14 , C30B25/183 , C30B25/186 , C30B29/06 , C30B33/12 , H01L21/02381 , H01L21/02395 , H01L21/02532 , H01L21/02576 , H01L21/02584 , H01L21/0262 , H01L21/02639 , H01L21/3065
摘要： An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.
摘要翻译：外延生长方法包括提供衬底材料的暴露的结晶区域。硅在低温工艺中外延沉积在衬底材料上，其中沉积温度低于500摄氏度。源气体用稀释气体稀释，稀释气体与原料气体的气体比小于1000。

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