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41. 发明授权

US06673663B2 Methods of forming field effect transistors and related field effect transistor constructions 失效
标题翻译：形成场效应晶体管和相关场效应晶体管结构的方法
公开(公告)号：US06673663B2
公开(公告)日：2004-01-06
申请号：US10143264
申请日：2002-05-08
申请人： Zhiqiang Wu , Paul Hatab
发明人： Zhiqiang Wu , Paul Hatab
IPC分类号： H01L218238
CPC分类号： H01L29/66583 , H01L29/1045 , H01L29/105 , H01L29/41775 , H01L29/66537 , H01L29/66553 , H01L29/66606 , H01L29/7833 , Y10S257/917
摘要： Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.
摘要翻译：描述形成场效应晶体管和相关场效应晶体管结构的方法。在半导体衬底上形成掩模层，并且通过其形成具有侧壁的开口。开口限定了要在其上形成场效应晶体管栅极的衬底区域。通过开口提供第一导电类型的掺杂剂并进入衬底。侧壁间隔件形成在开口的相应侧壁上。通过开口和衬底提供与第一导电类型不同的第二导电类型的增强掺杂剂。晶体管栅极形成在靠近侧壁间隔物的开口内，并且第二导电类型的源极/漏极区域可操作地在晶体管栅极附近扩散到衬底中。第一导电类型掺杂剂在晶体管的源极/漏极区域和轻掺杂漏极（LDD）区域附近形成晕圈。

42. 发明授权

US06545903B1 Self-aligned resistive plugs for forming memory cell with phase change material 有权
标题翻译：用于形成具有相变材料的存储单元的自对准电阻塞
公开(公告)号：US06545903B1
公开(公告)日：2003-04-08
申请号：US10023392
申请日：2001-12-17
申请人： Zhiqiang Wu
发明人： Zhiqiang Wu
IPC分类号： G11C1100
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： Memory devices are disclosed for storage and retrieval of information, wherein resistive plugs are provided above and below a phase change material to form a memory cell. The plugs may be formed by implanting regions in high resistivity material above and below a phase change material layer to lower the resistivity in the implanted regions.
摘要翻译：公开了用于存储和检索信息的存储器件，其中在相变材料的上方和下方提供电阻插塞以形成存储器单元。可以通过在相变材料层上方和下方的高电阻率材料中注入区域以降低注入区域中的电阻率来形成插塞。

43. 发明授权

US06414376B1 Method and apparatus for reducing isolation stress in integrated circuits 失效
标题翻译：降低集成电路隔离应力的方法和装置
公开(公告)号：US06414376B1
公开(公告)日：2002-07-02
申请号：US09252837
申请日：1999-02-19
申请人： Randhir P. S. Thakur , Kevin G. Donohoe , Zhiqiang Wu , Alan R. Reinberg
发明人： Randhir P. S. Thakur , Kevin G. Donohoe , Zhiqiang Wu , Alan R. Reinberg
IPC分类号： H01L2358
CPC分类号： H01L21/32 , H01L21/0332
摘要： Stress resulting from silicon nitride is diminished by forming an oxidation mask with silicon nitride having a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride by varying the amount of hydride, such as dichlorosilane (DCS), mixed with ammonia. The silicon nitride can be graded in a substantially linear or non-linear fashion. Silicon nitride formed with higher levels of DCS mixed with ammonia is referred to as silicon rich nitride because of its relatively higher silicon content. In one embodiment, the graded silicon nitride may be formed with one type of non-linear silicon grading, an abrupt junction. In other embodiments, the silicon nitride is formed in a variety of shapes fashioned during or after silicon nitride growth. In one embodiment, the stress from the silicon nitride is reduced by forming a polysilicon buffer layer between two silicon nitride layers. In another embodiment, the stress from the silicon nitride is reduced by forming the silicon nitride on a pad layer, which in turn is formed on a base layer.
摘要翻译：通过用具有梯度硅浓度的氮化硅形成氧化掩模来减小氮化硅产生的应力。通过改变与氨混合的氢化物（例如二氯硅烷（DCS））的量来改变氮化硅中的硅含量来实现分级。氮化硅可以以基本线性或非线性方式分级。由于硅含量相对较高，因此与氨混合的较高水平的DCS形成的氮化硅被称为富含氮的氮化物。在一个实施例中，渐变氮化硅可以用一种类型的非线性硅分级，突变结形成。在其它实施例中，氮化硅形成为在氮化硅生长期间或之后形成的各种形状。在一个实施例中，通过在两个氮化硅层之间形成多晶硅缓冲层来减小来自氮化硅的应力。在另一个实施方案中，通过在衬底层上形成氮化硅来降低来自氮化硅的应力，衬垫层又形成在基底层上。

44. 发明授权

US06406957B1 Methods of forming field effect transistors and related field effect transistor constructions 有权
标题翻译：形成场效应晶体管和相关场效应晶体管结构的方法
公开(公告)号：US06406957B1
公开(公告)日：2002-06-18
申请号：US09494973
申请日：2000-01-31
申请人： Zhiqiang Wu , Paul Hatab
发明人： Zhiqiang Wu , Paul Hatab
IPC分类号： H01L218238
CPC分类号： H01L29/66583 , H01L29/1045 , H01L29/105 , H01L29/41775 , H01L29/66537 , H01L29/66553 , H01L29/66606 , H01L29/7833 , Y10S257/917
摘要： Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.
摘要翻译：描述形成场效应晶体管和相关场效应晶体管结构的方法。在半导体衬底上形成掩模层，并且通过其形成具有侧壁的开口。开口限定了要在其上形成场效应晶体管栅极的衬底区域。通过开口提供第一导电类型的掺杂剂并进入衬底。侧壁间隔件形成在开口的相应侧壁上。通过开口和衬底提供与第一导电类型不同的第二导电类型的增强掺杂剂。晶体管栅极形成在靠近侧壁间隔物的开口内，并且第二导电类型的源极/漏极区域可操作地在晶体管栅极附近扩散到衬底中。第一导电类型掺杂剂在晶体管的源极/漏极区域和轻掺杂漏极（LDD）区域附近形成晕圈。

45. 发明授权

US06264486B1 Zero insertion force sockets using negative thermal expansion materials 失效
标题翻译：使用负热膨胀材料的零插入插座
公开(公告)号：US06264486B1
公开(公告)日：2001-07-24
申请号：US09630977
申请日：2000-08-02
申请人： Tongbi Jiang , Zhiqiang Wu
发明人： Tongbi Jiang , Zhiqiang Wu
IPC分类号： H01R1320
CPC分类号： H01R12/82 , H01R12/58 , H05K1/0271 , H05K1/112 , H05K3/28 , H05K3/3421 , H05K3/3436 , H05K3/3452 , H05K2201/0195 , H05K2201/068 , H05K2201/09472 , Y10S439/932
摘要： A socket device for receiving a connection pin is disclosed, the socket device including a substrate having an upper surface. The socket device includes a connection pad disposed on the upper surface and a first layer disposed on the upper surface and on the connection pad. The first layer includes material having an overall positive coefficient of thermal expansion. The socket device includes a second layer disposed on the first layer. The second layer includes material having an overall negative coefficient of thermal expansion. The socket device also includes a contact hole formed in the first and second layers exposing a portion of the connection pad.
摘要翻译：公开了一种用于接收连接销的插座装置，插座装置包括具有上表面的基板。插座装置包括设置在上表面上的连接垫和设置在上表面上和连接垫上的第一层。第一层包括具有总体正的热膨胀系数的材料。插座装置包括设置在第一层上的第二层。第二层包括具有总体负的热膨胀系数的材料。插座装置还包括形成在第一和第二层中的接触孔，露出连接垫的一部分。

46. 发明授权

US6073497A High resolution pressure sensing device having an insulating flexible matrix loaded with filler particles 失效
公开(公告)号：US6073497A
公开(公告)日：2000-06-13
申请号：US906583
申请日：1997-08-05
申请人： Tongbi Jiang , Zhiqiang Wu
发明人： Tongbi Jiang , Zhiqiang Wu
IPC分类号： G01L1/20 , G01L1/16
CPC分类号： G01L1/205
摘要： A high-resolution pressure-sensing device is disclosed. The device includes an insulating flexible matrix having a plurality of filler particles. Application of a force to the matrix causes compression of the matrix. This results in the filler particles occupying a greater amount of space within the matrix relative to when no force is applied. A detector attached to the matrix detects or measures the volume of the filler particles relative to the volume of the matrix, and therefore determines the force applied to the matrix. Preferably, the resistivity of the matrix is inversely proportional to the volume percent of the filler particles, in which case the detector is a resistance-measuring circuit.

47. 发明授权

US09436362B2 OData service provisioning on top of GenIL layer 有权
公开(公告)号：US09436362B2
公开(公告)日：2016-09-06
申请号：US14596933
申请日：2015-01-14
申请人： Zhiqiang Wu , Christian Weiss , Joerg Singler
发明人： Zhiqiang Wu , Christian Weiss , Joerg Singler
IPC分类号： G06F17/30 , G06F3/0484 , H04L29/08
CPC分类号： G06F3/0484 , G06F17/30569 , G06F17/30876 , H04L67/10 , H04L67/32
摘要： The disclosure generally describes computer-implemented methods, software, and systems for allowing provisioning of open data protocol (OData) services on top of a generic interaction layer (GenIL). One computer-implemented method includes receiving an OData-compliant request for data, determining a GenIL data provider to receive the OData-compliant request for data, determining the memory location of the data, requesting the data from the determined memory location, receiving the requested data from the determined memory location, converting, using at least one computer, the received data into an OData-compliant format, rendering an OData-compliant response, and transmitting the OData-compliant response.

48. 发明申请

US20150134683A1 ODATA SERVICE PROVISIONING ON TOP OF GENIL LAYER 有权
公开(公告)号：US20150134683A1
公开(公告)日：2015-05-14
申请号：US14596933
申请日：2015-01-14
申请人： Zhiqiang Wu , Christian Weiss , Joerg Singler
发明人： Zhiqiang Wu , Christian Weiss , Joerg Singler
IPC分类号： G06F17/30 , H04L29/08
CPC分类号： G06F3/0484 , G06F17/30569 , G06F17/30876 , H04L67/10 , H04L67/32
摘要： The disclosure generally describes computer-implemented methods, software, and systems for allowing provisioning of open data protocol (OData) services on top of a generic interaction layer (GenIL). One computer-implemented method includes receiving an OData-compliant request for data, determining a GenIL data provider to receive the OData-compliant request for data, determining the memory location of the data, requesting the data from the determined memory location, receiving the requested data from the determined memory location, converting, using at least one computer, the received data into an OData-compliant format, rendering an OData-compliant response, and transmitting the OData-compliant response.

49. 发明授权

US08987824B2 Multi-gate semiconductor devices 有权
标题翻译：多栅极半导体器件
公开(公告)号：US08987824B2
公开(公告)日：2015-03-24
申请号：US13301873
申请日：2011-11-22
申请人： Jon-Hsu Ho , Chih-Ching Wang , Ching-Fang Huang , Wen-Hsing Hsieh , Tsung-Hsing Yu , Yi-Ming Sheu , Chih-Chieh Yeh , Ken-Ichi Goto , Zhiqiang Wu
发明人： Jon-Hsu Ho , Chih-Ching Wang , Ching-Fang Huang , Wen-Hsing Hsieh , Tsung-Hsing Yu , Yi-Ming Sheu , Chih-Chieh Yeh , Ken-Ichi Goto , Zhiqiang Wu
IPC分类号： H01L27/12 , H01L27/092 , H01L29/78 , H01L29/10
CPC分类号： H01L27/0886 , H01L27/0924 , H01L29/105 , H01L29/7831 , H01L29/7833 , H01L29/785 , H01L29/7851
摘要： A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.
摘要翻译：形成包括半导体衬底的多栅极半导体器件。多栅半导体器件还包括第一晶体管，其包括在半导体衬底之上延伸的第一鳍部。第一晶体管具有形成在其中的第一沟道区。第一沟道区域包括以第一掺杂剂类型的第一浓度掺杂的第一沟道区域部分和以第一掺杂剂类型的第二浓度掺杂的第二沟道区域部分。第二浓度高于第一浓度。第一晶体管还包括形成在第一沟道区上的第一栅电极层。第一栅极电极层可以是第二掺杂剂类型。第一掺杂剂类型可以是N型，第二掺杂剂类型可以是P型。第二沟道区域部分可以形成在第一沟道区域部分上。

50. 发明授权

US08623716B2 Multi-gate semiconductor devices and methods of forming the same 有权
标题翻译：多栅半导体器件及其形成方法
公开(公告)号：US08623716B2
公开(公告)日：2014-01-07
申请号：US13288047
申请日：2011-11-03
申请人： Chih-Ching Wang , Jon-Hsu Ho , Ching-Fang Huang , Wen-Hsing Hsieh , Tsung-Hsing Yu , Yi-Ming Sheu , Ken-Ichi Goto , Zhiqiang Wu
发明人： Chih-Ching Wang , Jon-Hsu Ho , Ching-Fang Huang , Wen-Hsing Hsieh , Tsung-Hsing Yu , Yi-Ming Sheu , Ken-Ichi Goto , Zhiqiang Wu
IPC分类号： H01L21/00 , H01L21/338 , H01L21/336 , H01L21/3205
CPC分类号： H01L29/7855 , H01L21/823431 , H01L21/823821 , H01L27/0886 , H01L27/0924 , H01L29/66795 , H01L29/785
摘要： A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.
摘要翻译：一种多栅半导体器件及其制造方法。形成多栅半导体器件，其包括形成在具有第一掺杂剂类型的半导体衬底上的第一晶体管的第一鳍。第一晶体管具有第一掺杂剂类型的掺杂沟道区。该器件还包括形成在第一掺杂剂型半导体衬底上的第二晶体管的第二鳍。第二晶体管具有第二掺杂剂类型的掺杂沟道区。该器件还包括形成在第一鳍片的沟道区域上的第二掺杂剂类型的栅极电极层和形成在第二鳍片的沟道区域上的第一掺杂剂类型的栅极电极层。

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