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    • 46. 发明授权
    • Use of a colorant solution containing a stable, at least partially neutralized chromium (III) coordination compound for coloring unglazed ceramic
    • 使用含有稳定的,至少部分中和的铬(III)配位化合物的着色剂溶液用于着色无釉陶瓷
    • US06352587B1
    • 2002-03-05
    • US09323140
    • 1999-06-01
    • Thomas StaffelJürgen StraubThomas Klein
    • Thomas StaffelJürgen StraubThomas Klein
    • C09C134
    • C04B41/5033
    • A process for coloring an unglazed ceramic with an aqueous colorant solution containing a chromium (III) coordination compound which is at least partially neutralized and stable, including (a) dissolving a carboxylic acid selected from the group consisting of acetic acid, an organic dicarboxylic acid having a general formula (COOH)—(CH2)n—(COOH), where n ranges from 0 to 10, and an unsaturated, organic dicarboxylic acid in water at a temperature ranging from 40 to 60° C. to provide an aqueous solution of a carboxylic acid; (b) adding a chromium (III) compound to the aqueous solution of a carboxylic acid while stirring for a time and at a temperature effective for reaction to form an aqueous solution containing a chromium (III) coordination compound; (c) filtering the aqueous solution containing the chromium (III) coordination compound to provide a filtered aqueous solution; and (d) adjusting pH of the filtered aqueous solution to a pH ranging from 3 to 6.5 by addition of one of alkali hydroxide or ammonia to provide the aqueous colorant solution containing a chromium (III) coordination compound which is at least partially neutralized, which is stable, and which has a chromium content ranging from 5 to 10% by weight.
    • 一种用含有至少部分中和并稳定的铬(III)配位化合物的含水着色剂溶液着色无釉陶瓷的方法,包括(a)将选自乙酸,有机二羧酸 具有通式(COOH) - (CH 2)n - (COOH),其中n为0至10,以及在40至60℃的温度范围内的不饱和有机二羧酸在水中的溶液,以提供水溶液 的羧酸; (b)向羧酸水溶液中加入铬(III)化合物,同时搅拌一段时间并在有效反应的温度下形成含有(III)配位化合物的水溶液; (c)过滤含有铬(III)配位化合物的水溶液以提供过滤的水溶液; 和(d)通过加入碱金属氢氧化物或氨来调节过滤的水溶液的pH至3至6.5的pH,以提供含有至少部分中和的铬(III)配位化合物的含水着色剂溶液,其中 是稳定的,并且其铬含量为5至10重量%。
    • 47. 发明授权
    • Aqueous ruthenium chloride solution for blackening ceramic surfaces
    • 用于使陶瓷表面变黑的氯化钌水溶液
    • US6042884A
    • 2000-03-28
    • US11898
    • 1998-04-30
    • Thomas KleinThomas StaffelLysander Fischer
    • Thomas KleinThomas StaffelLysander Fischer
    • C04B33/34C04B41/50C04B41/85C04B41/87B05D3/02
    • C04B41/009C04B33/34C04B41/5072C04B41/85C04B2111/82
    • An aqueous ruthenium chloride solution for blackening ceramic surfaces includes ruthenium chloride; water present in an amount effective to provide an aqueous solution of ruthenium chloride; and a buffer which is selected from the group consisting of sodium acetate, sodium propionate, potassium acetate, potassium propionate, and mixtures thereof, and which is present in an amount effective to provide the aqueous solution with a pH of at least 1.5. A method for dyeing a ceramic surface includes applying the aqueous solution of ruthenium chloride to a ceramic surface by at least one of spraying, dipping, painting and printing to provide a treated surface; drying and firing the treated surface at a temperature ranging from about 300 to about 1400.degree. C. for a period of time ranging from one half hour to five hours; and grinding and polishing the treated surface to even out the treated surface.
    • PCT No.PCT / EP97 / 03087第 371日期:1998年4月30日 102(e)日期1998年4月30日PCT提交1997年6月13日PCT公布。 公开号WO97 / 49650 PCT 日期1997年12月31日用于使陶瓷表面变黑的氯化钌水溶液包括氯化钌; 以有效提供氯化钌水溶液的量存在水; 和选自乙酸钠,丙酸钠,乙酸钾,丙酸钾及其混合物的缓冲剂,其以有效提供水溶液至少1.5的pH的量存在。 用于染色陶瓷表面的方法包括通过喷涂,浸涂,喷涂和印刷中的至少一种将氯化钌水溶液施加到陶瓷表面以提供经处理的表面; 在约300至约1400℃的温度下干燥和烧制经处理的表面一段时间为半小时至五小时; 并研磨和抛光经处理的表面以使经处理的表面均匀。
    • 48. 发明授权
    • Dynamic MOS RAM with storage cells having a mainly insulated first plate
    • 具有存储单元的动态MOS RAM具有主要绝缘的第一板
    • US4475118A
    • 1984-10-02
    • US217425
    • 1980-12-15
    • Thomas KleinCharles E. Boettcher
    • Thomas KleinCharles E. Boettcher
    • H01L27/108H01L27/04G11C11/40
    • H01L27/10805
    • An improved dynamic MOS RAM having a plurality of selection lines and data lines and a plurality of storage cells connected thereto, wherein each storage cell includes a storage capacitor having first and second plates, wherein the second plate is adapted to be coupled to a reference potential terminal; and a MOSFET having a semiconductor substrate, a gate connected to one of the selection lines, a first conduction terminal coupled to one of the data lines, and a second conduction terminal connected in common with a first plate of the storage capacitor, is disclosed. The first plate of the storage capacitor includes first doped polysilicon conductive layer that has the majority of its area separated from the semiconductor substrate of the MOSFET by at least an insulating layer. The second plate of the storage capacitor includes a second doped polysilicon conductive layer that is at least coextensive with and insulated from the first conductive layer. The transistor gate is defined by a third doped polysilicon conductive layer that is insulated from the first and second conductive layers. Approximately 45% of the cell area can be utilized for charge storage, and only about 20% of this storage area is susceptible to loss of charge by reason of leakage through the depletion/junction area in the substrate.
    • 一种改进的动态MOS RAM,具有多个选择线和数据线以及连接到其上的多个存储单元,其中每个存储单元包括具有第一和第二板的存储电容器,其中第二板适于耦合到参考电位 终奌站; 以及具有半导体衬底的MOSFET,连接到选择线之一的栅极,耦合到数据线之一的第一导电端子和与存储电容器的第一板共同连接的第二导电端子。 存储电容器的第一板包括第一掺杂多晶硅导电层,其第一掺杂多晶硅导电层的绝大部分区域通过至少绝缘层与MOSFET的半导体衬底分离。 存储电容器的第二板包括与第一导电层至少共同延伸并与其绝缘的第二掺杂多晶硅导电层。 晶体管栅极由与第一和第二导电层绝缘的第三掺杂多晶硅导电层限定。 大约45%的电池区域可以用于电荷存储,并且由于通过衬底中的耗尽/结合区域的泄漏,该存储区域的约20%容易损失电荷。
    • 49. 发明授权
    • Method of making integrated semiconductor structure having an MOS and a
capacitor device
    • US4290186A
    • 1981-09-22
    • US059637
    • 1979-07-23
    • Thomas KleinAndrew G. VaradiCharles E. Boettcher
    • Thomas KleinAndrew G. VaradiCharles E. Boettcher
    • H01L21/8242H01L27/108H01L29/94B01J17/00H01L21/265
    • H01L27/1085H01L27/10805H01L29/94
    • This disclosure is directed to an improved semiconductor capacitor structure especially useful in an integrated semiconductor structure with an MOS device and fabrication methods therefor. This semiconductor capacitor is particularly useful for forming the capacitor portion of a single MOS memory cell structure in a dynamic MOS random access memory which utilizes one MOS device in combination with a capacitor. In one specific disclosure embodiment, the semiconductor capacitor comprises a boron (P) implanted region in a substrate of P- type conductivity followed by a shallow arsenic (N) implant into the boron implanted region. The boron implanted region provides a P type conductivity which has a higher concentration of P type impurities than the concentration of impurities contained in the substrate which is of P- type conductivity. Thus, the boron implanted region performs the important function of preventing a surface N type inversion layer from being formed across the semiconductor surface beneath the silicon dioxide insulating layer which could occur across the substrate P- surface if the arsenic implant region was made into the P- substrate without the P type boron implant. The arsenic implant is of N type conductivity and has a higher concentration of impurities than the boron implant region. The dielectric portion of the semiconductor capacitor is the portion of the silicon dioxide layer located on the surface of the arsenic implanted region. A doped polysilicon electrode is formed over this portion of the silicon dioxide insulating layer and provides the other plate of the capacitor structure. In another embodiment that is disclosed, this above described semiconductor capacitor structure or device is combined with an MOS device in a single integrated semiconductor structure in order to provide a single MOS memory cell for dynamic random access memory chip utilizing the MOS device and the capacitor. Preferably, the semiconductor capacitor is shown as a connected extension of either the source or drain region of the MOS device.