专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20070273416A1 Signal delay loop and method for locking a signal delay loop 审中-公开
标题翻译：信号延迟环路和锁定信号延迟环路的方法
公开(公告)号：US20070273416A1
公开(公告)日：2007-11-29
申请号：US11805899
申请日：2007-05-25
申请人： Patrick Heyne
发明人： Patrick Heyne
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/07 , H03L7/0814
摘要： A signal delay loop (1) having a first signal delay line (4) which has a plurality of series-connectable signal delay elements with a respective associated component signal delay time (ΔTVE), where the first signal delay line (4) outputs an input signal, applied to a signal input (2) of the signal delay loop (1), with a time delay to a signal output (3) of the signal delay loop (1); a second signal delay line (5) which feeds back the signal which is output on the signal output (3) of the signal delay loop (1) to a phase detector (6) which detects a phase difference (Δφ) between the feedback signal and the input signal; a control unit (7) which takes the detected phase difference (Δφ) as a basis for connecting a portion of the signal delay elements in the first signal delay line (4) in series to set a total signal delay time for the first signal delay line (4); where the respective component signal delay time (ΔTVE) of each signal delay element in the first signal delay line (4) is adjustable.
摘要翻译：一种具有第一信号延迟线（4）的信号延迟回路（1），该第一信号延迟线（4）具有多个具有相应的相关分量信号延迟时间（DeltaT VE）的可串联的信号延迟元件，其中第一信号延迟线（4）以对信号延迟回路（1）的信号输出（3）的时间延迟输出施加到信号延迟回路（1）的信号输入端（2）的输入信号; 第二信号延迟线（5），将在信号延迟环（1）的信号输出（3）上输出的信号反馈到相位检测器（6），该相位检测器检测反馈信号之间的相位差（Deltaphi）和输入信号; 将检测到的相位差（Deltaphi）作为将第一信号延迟线（4）中的信号延迟元件的一部分串联连接的基础的控制单元（7），以设定第一信号延迟的总信号延迟时间行（4）; 其中第一信号延迟线（4）中的每个信号延迟元件的相应分量信号延迟时间（DeltaT VE）可调。

42. 发明授权

US07126401B2 Integratable, controllable delay device, use of a delay device, as well as an integratable multiplexer for use in a delay device 有权
标题翻译：可集成的，可控制的延迟装置，延迟装置的使用，以及用于延迟装置的可积分多路复用器
公开(公告)号：US07126401B2
公开(公告)日：2006-10-24
申请号：US11077374
申请日：2005-03-11
申请人： Patrick Heyne , Musa Saglam
发明人： Patrick Heyne , Musa Saglam
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00058 , H03K2005/00156 , H03K2005/00208
摘要： A delay device has series-connected multiplexers in a differential form. First connections of the multiplexers are connected to the output of an upstream multiplexer. Second inputs of the multiplexers are connected to the input connection to which the signal to be delayed can be supplied. A control signal controls the switch setting of one of the multiplexers such that its output is connected to the input of the delay device. The other multiplexers have the other switch setting. In consequence, a specific delay time is set for the delay device. The multiplexers have four current paths which are coupled in pairs. One of the current path pairs can be decoupled from the current source via a transistor.
摘要翻译：延迟装置具有差分形式的串联多路复用器。多路复用器的第一连接连接到上游多路复用器的输出端。多路复用器的第二输入端连接到可被提供延迟信号的输入端。控制信号控制多路复用器之一的开关设置，使得其输出连接到延迟装置的输入端。其他多路复用器具有另一个开关设置。因此，为延迟装置设定特定的延迟时间。多路复用器具有成对耦合的四个电流路径。电流路径对之一可以通过晶体管与电流源解耦。

43. 发明申请

US20060214709A1 Circuit arrangement for generating a synchronization signal 审中-公开
标题翻译：用于产生同步信号的电路装置
公开(公告)号：US20060214709A1
公开(公告)日：2006-09-28
申请号：US11375569
申请日：2006-03-15
申请人： Aaron Nygren , Patrick Heyne
发明人： Aaron Nygren , Patrick Heyne
IPC分类号： H03L7/06
CPC分类号： H04L7/0337
摘要： A circuit arrangement is provided for generating a synchronization signal having signal edge changes whose timings are defined. The arrangement includes a plurality of controllable signal delay arrangements, each including a circuit part with variable signal delay and a circuit part with constant signal delay, where an input signal is supplied to a first controllable signal delay arrangement, a phase detection device including two inputs and one output, and a control circuit that controls the circuit parts with variable signal delay. The input of the control circuit is connected to the output of the phase detection device, and the output of the control circuit is connected to control inputs of the circuit parts with variable signal delay. The input signal is also supplied to the first input of the phase detection device. One output of one of the controllable signal delay arrangements is connected to the second input of the phase detection device. At least one of the controllable signal delay arrangements produces a synchronization signal at the output of the circuit part with variable signal delay.
摘要翻译：提供了一种电路装置，用于产生具有定义其定时的信号沿变化的同步信号。该装置包括多个可控信号延迟装置，每个可控信号延迟装置包括具有可变信号延迟的电路部分和具有恒定信号延迟的电路部分，其中输入信号被提供给第一可控信号延迟装置，相位检测装置包括两个输入和一个输出，以及控制电路，其具有可变的信号延迟。控制电路的输入端连接到相位检测装置的输出端，控制电路的输出端与可变信号延迟的电路部分的控制输入相连。输入信号也被提供给相位检测装置的第一输入端。可控信号延迟装置之一的一个输出端连接到相位检测装置的第二输入端。可控信号延迟装置中的至少一个在具有可变信号延迟的电路部分的输出处产生同步信号。

44. 发明授权

US06529028B1 Configuration for testing a plurality of memory chips on a wafer 有权
标题翻译：用于测试晶片上的多个存储器芯片的配置
公开(公告)号：US06529028B1
公开(公告)日：2003-03-04
申请号：US09302649
申请日：1999-04-30
申请人： Dieter Härle , Patrick Heyne , Martin Buck
发明人： Dieter Härle , Patrick Heyne , Martin Buck
IPC分类号： G01R3128
CPC分类号： G11C29/006 , G11C29/26 , G11C29/48 , G11C29/56
摘要： A configuration for testing a plurality of memory chips on a wafer, in which needles are used to supply the memory chips with supply voltages, an initialization signal, a read signal, a clock signal as well as address, data and control signals. The address, data and control signals are in this case produced by a logic device disposed in an edge area of the memory chip and are supplied directly to the memory chips.
摘要翻译：用于测试晶片上的多个存储器芯片的配置，其中针被用于向存储器芯片提供电源电压，初始化信号，读取信号，时钟信号以及地址，数据和控制信号。在这种情况下，地址，数据和控制信号由设置在存储器芯片的边缘区域中的逻辑器件产生并被直接提供给存储器芯片。

45. 发明申请

US20070285139A1 Amplifier Circuit and Method for Correcting the Duty Ratio of a Differential Clock Signal 审中-公开
标题翻译：用于校正差分时钟信号的占空比的放大器电路和方法
公开(公告)号：US20070285139A1
公开(公告)日：2007-12-13
申请号：US11748703
申请日：2007-05-15
申请人： Patrick Heyne
发明人： Patrick Heyne
IPC分类号： H03K3/017
CPC分类号： H03K5/2481 , H03K5/151 , H03K5/1565 , H03K2005/00228
摘要： An amplifier circuit is configured to correct the duty ratio of a differential clock signal to a desired value of 50% via a differential amplifier including a MOS transistor pair. The clock signal to be corrected is applied to a respective gate terminal of the MOS transistor pair of the amplifier circuit, a differential analog duty ratio correction signal is generated by in each case integrating the true and complementary clock signal delivered by each MOS transistor at a source/drain terminal. The differential duty ratio correction signal is in each case applied to the electrically separated substrate terminals of the MOS transistor pair so that the substrate voltages, and thus the turn-on voltages of the MOS transistors of the transistor pair are in each case conversely influenced.
摘要翻译：放大器电路经由包括MOS晶体管对的差分放大器将差分时钟信号的占空比校正为50％的期望值。要校正的时钟信号被施加到放大器电路的MOS晶体管对的相应的栅极端子，通过在每个情况下产生差分模拟占空比校正信号，将由每个MOS晶体管传递的真实和互补时钟信号集成在源极/漏极端子。差分占空比校正信号在每种情况下都被施加到MOS晶体管对的电分离的衬底端子，使得晶体管对的MOS晶体管的导通电压在每种情况下都相反地受到影响。

46. 发明申请

US20050218954A1 Integratable, controllable delay device, use of a delay device, as well as an integratable multiplexer for use in a delay device 有权
标题翻译：可集成的，可控制的延迟装置，延迟装置的使用，以及用于延迟装置的可积分多路复用器
公开(公告)号：US20050218954A1
公开(公告)日：2005-10-06
申请号：US11077374
申请日：2005-03-11
申请人： Patrick Heyne , Musa Saglam
发明人： Patrick Heyne , Musa Saglam
IPC分类号： G11C11/407 , H03H11/26 , H03K5/00 , H03K5/13 , H03K5/14
CPC分类号： H03K5/133 , H03K2005/00058 , H03K2005/00156 , H03K2005/00208
摘要： A delay device has series-connected multiplexers in a differential form. First connections of the multiplexers are connected to the output of an upstream multiplexer. Second inputs of the multiplexers are connected to the input connection to which the signal to be delayed can be supplied. A control signal controls the switch setting of one of the multiplexers such that its output is connected to the input of the delay device. The other multiplexers have the other switch setting. In consequence, a specific delay time is set for the delay device. The multiplexers have four current paths which are coupled in pairs. One of the current path pairs can be decoupled from the current source via a transistor.
摘要翻译：延迟装置具有差分形式的串联多路复用器。多路复用器的第一连接连接到上游多路复用器的输出端。多路复用器的第二输入端连接到可被提供延迟信号的输入端。控制信号控制多路复用器之一的开关设置，使得其输出连接到延迟装置的输入端。其他多路复用器具有另一个开关设置。因此，为延迟装置设定特定的延迟时间。多路复用器具有成对耦合的四个电流路径。电流路径对之一可以通过晶体管与电流源解耦。

47. 发明授权

US06573754B2 Circuit configuration for enabling a clock signal in a manner dependent on an enable signal 有权
公开(公告)号：US06573754B2
公开(公告)日：2003-06-03
申请号：US10125088
申请日：2002-04-18
申请人： Ullrich Menczigar , Patrick Heyne
发明人： Ullrich Menczigar , Patrick Heyne
IPC分类号： H03K1900
CPC分类号： H03K5/1252 , H03K19/0016
摘要： A circuit configuration for enabling a clock signal in a manner dependent on an enable signal has first and second signal paths that are fed to a NAND gate. The second signal path contains an RS flip-flop, upstream of which NAND gates are connected, which, for their part, are connected via different inverters to the input terminals for the clock signal and the enable signal, respectively.

48. 发明授权

US06194928B1 Integrated circuit with adjustable delay unit 有权
标题翻译：具有可调延时单元的集成电路
公开(公告)号：US06194928B1
公开(公告)日：2001-02-27
申请号：US09408687
申请日：1999-09-30
申请人： Patrick Heyne
发明人： Patrick Heyne
IPC分类号： H03L700
CPC分类号： H03K5/131 , H03K5/133 , H03L7/0814 , H03L7/089
摘要： The delay unit has first delay elements each having a first delay time and second delay elements each having a second delay time. The second delay time is greater than the first delay time. A control unit controls the delay time of the delay unit by, first, incrementally increasing or by incrementally reducing the number of second delay elements in the signal path and thereby altering the actual value of the delay in the direction towards a desired (setpoint) value until the desired value is exceeded. The control unit then, by incrementally reducing or increasing, respectively, the number of first delay elements in the signal path, alters the actual value of the delay in the direction towards the desired value until the desired value is exceeded once more. In the event of subsequent changes in the desired value or in the actual value, the number of first delay elements is incrementally altered, while the number of second delay elements in the signal path is kept constant.
摘要翻译：延迟单元具有每个具有第一延迟时间的第一延迟元件和每个具有第二延迟时间的第二延迟元件。第二延迟时间大于第一延迟时间。控制单元首先通过逐渐增加或递增地减少信号路径中的第二延迟元件的数量来控制延迟单元的延迟时间，从而改变朝着期望（设定值）值的方向上的延迟的实际值直到超过所需值。然后，控制单元通过递增地减小或增加信号路径中的第一延迟元件的数量，改变朝向期望值的方向上的延迟的实际值，直到超过期望值。在期望值或实际值的随后变化的情况下，第一延迟元件的数量被逐渐改变，而信号路径中的第二延迟元件的数量保持恒定。

49. 发明授权

US06191627B1 Integrated circuit having adjustable delay units for clock signals 有权
标题翻译：集成电路具有用于时钟信号的可调延迟单元
公开(公告)号：US06191627B1
公开(公告)日：2001-02-20
申请号：US09408685
申请日：1999-09-30
申请人： Patrick Heyne
发明人： Patrick Heyne
IPC分类号： H03L700
CPC分类号： H03L7/0805 , H03L7/0812
摘要： An integrated circuit includes a first adjustable delay unit to which a first clock signal is fed and a second adjustable delay unit to which a second clock signal is fed. A phase detector is connected to the input and to the output of the first delay unit. A control unit serves for correcting a phase difference obtained by the phase detector and controls the delay time of the first delay unit in a corresponding manner. The control unit additionally sets the delay time of the second delay unit to essentially the same value as that of the first delay unit. Furthermore, the output of the second delay unit is connected to the input of a third adjustable delay unit.
摘要翻译：集成电路包括第一可调延迟单元，第一时钟信号被馈送到第一可调延迟单元和第二可调延迟单元，第二时钟信号被馈送到第二可调延迟单元。相位检测器连接到第一延迟单元的输入端和输出端。控制单元用于校正由相位检测器获得的相位差，并且以相应的方式控制第一延迟单元的延迟时间。控制单元另外将第二延迟单元的延迟时间设置为与第一延迟单元基本相同的值。此外，第二延迟单元的输出连接到第三可调延迟单元的输入。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式