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41. 发明申请

US20120018863A1 MICROELECTRONIC ELEMENTS WITH REAR CONTACTS CONNECTED WITH VIA FIRST OR VIA MIDDLE STRUCTURES 有权
标题翻译：具有通过第一个或通过中间结构连接的后接触器的微电子元件
公开(公告)号：US20120018863A1
公开(公告)日：2012-01-26
申请号：US12842651
申请日：2010-07-23
申请人： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Piyush Savalia
发明人： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Piyush Savalia
IPC分类号： H01L23/528 , H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/16 , H01L25/0657 , H01L2224/02372 , H01L2224/02375 , H01L2224/02377 , H01L2224/0401 , H01L2224/05548 , H01L2224/06166 , H01L2224/06181 , H01L2224/13024 , H01L2224/131 , H01L2224/13111 , H01L2224/1329 , H01L2224/133 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/81801 , H01L2224/8182 , H01L2224/8185 , H01L2224/94 , H01L2924/014 , H01L2924/00014 , H01L2224/03 , H01L2224/81
摘要： A microelectronic unit includes a microelectronic element, e.g., an integrated circuit chip, having a semiconductor region of monocrystalline form. The semiconductor region has a front surface extending in a first direction, an active circuit element adjacent the front surface, a rear surface remote from the front surface, and a conductive via which extends towards the rear surface. The conductive via can be insulated from the semiconductor region by an inorganic dielectric layer. An opening can extend from the rear surface partially through a thickness of the semiconductor region, with the opening and the conductive via having respective widths in the first direction. The width of the opening may be greater than the width of the conductive via where the opening meets the conductive via. A rear contact can be electrically connected to the conductive via and exposed at the rear surface for electrical connection with an external circuit element, such as another like microelectronic unit, a microelectronic package, or a circuit panel.
摘要翻译：微电子单元包括具有单晶形式的半导体区域的微电子元件，例如集成电路芯片。半导体区域具有在第一方向上延伸的前表面，邻近前表面的有源电路元件，远离前表面的后表面和朝向后表面延伸的导电通孔。导电通孔可以通过无机介电层与半导体区域绝缘。开口可以从后表面部分地延伸穿过半导体区域的厚度，其中开口和导电通孔在第一方向上具有相应的宽度。开口的宽度可以大于导电通孔的宽度，其中开口与导电通孔相接。后触点可以电连接到导电通孔并在后表面暴露以与外部电路元件（例如另一个类似的微电子单元，微电子封装或电路板）电连接。

42. 发明申请

US20070148819A1 Microelectronic assemblies having very fine pitch stacking 有权
标题翻译：微电子组件具有非常细的间距堆积
公开(公告)号：US20070148819A1
公开(公告)日：2007-06-28
申请号：US11318164
申请日：2005-12-23
申请人： Belgacem Haba , Craig Mitchell
发明人： Belgacem Haba , Craig Mitchell
IPC分类号： H01L21/00 , H01L21/44
CPC分类号： H01L25/50 , H01L25/0657 , H01L25/105 , H01L2224/16 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/3011 , H01L2924/3511
摘要： A microelectronic assembly includes two or more microelectronic packages stacked at a fine pitch, which is finer than the pitch that is possible when using solder balls for making the joint. Each stackable package desirably includes a substrate having pins projecting from one surface of the substrate and solder balls projecting from the other surface of the substrate. Each stackable package may have one or more die attached to one or more of the surfaces of the substrate. In certain embodiments, die may be attached to both surfaces of the substrate. The dies may be electrically interconnected with the substrate using wire bonds, flip chip bonding, leads and/or stud bumping. The die may be encapsulated in an encapsulated material, under-filled or glob topped. In certain preferred embodiments, the combination of the conductive post height and ball height is equal to or greater than the height of the encapsulated or molded chip structure. The combination of the conductive post height and the ball height must be at least equal to the height of the encapsulated chip structure so that the conductive elements are able to span the gap between layers of the assembly. After the tips of the conductive pads are in contact with the solder masses, the solder masses are reflowed to form a permanent electrical interconnection between the stacked microelectronic packages. During reflow, the reflowed solder will wick up around the conductive posts to form elongated solder columns. In addition, when the solder is reflowed, surface tension pulls the opposing layers of the assembly toward one another and provides a self-centering action for the conductive posts.
摘要翻译：微电子组件包括以细间距堆叠的两个或更多个微电子封装，其比使用用于制造接头的焊球可能的间距更细。每个可堆叠封装理想地包括具有从基板的一个表面突出的销和从该基板的另一个表面突出的焊球的基板。每个可堆叠的封装可以具有一个或多个管芯附接到衬底的一个或多个表面。在某些实施例中，管芯可以附接到衬底的两个表面。模具可以使用引线接合，倒装芯片接合，引线和/或螺柱凸起与基板电互连。芯片可以封装在封装的材料中，未充满的或者顶部的。在某些优选实施例中，导电柱高度和球高度的组合等于或大于封装或模制芯片结构的高度。导电柱高度和球高度的组合必须至少等于封装的芯片结构的高度，使得导电元件能够跨越组件的层之间的间隙。在导电焊盘的尖端与焊料块接触之后，焊料质量被回流以在堆叠的微电子封装之间形成永久的电互连。在回流期间，回流的焊料将在导电柱周围吸收，形成细长的焊料柱。此外，当焊料回流时，表面张力将组件的相对的层相互拉向彼此，并为导电柱提供自对中动作。

43. 发明申请

US20070096295A1 Back-face and edge interconnects for lidded package 审中-公开
公开(公告)号：US20070096295A1
公开(公告)日：2007-05-03
申请号：US11641141
申请日：2006-12-19
申请人： Robert Burtzlaff , Belgacem Haba , Giles Humpston , David Tuckerman , Michael Warner , Craig Mitchell
发明人： Robert Burtzlaff , Belgacem Haba , Giles Humpston , David Tuckerman , Michael Warner , Craig Mitchell
IPC分类号： H01L23/12
CPC分类号： H01L23/3114 , B81B2207/095 , B81C1/00293 , B81C1/00301 , B81C2203/0118 , B81C2203/0145 , B81C2203/019 , H01L21/76898 , H01L23/04 , H01L24/11 , H01L24/13 , H01L24/48 , H01L27/14618 , H01L27/14627 , H01L27/14636 , H01L33/62 , H01L2224/0401 , H01L2224/05624 , H01L2224/05644 , H01L2224/11 , H01L2224/11334 , H01L2224/13 , H01L2224/13099 , H01L2224/131 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13169 , H01L2224/1401 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/4824 , H01L2224/48247 , H01L2224/484 , H01L2224/81801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01058 , H01L2924/01061 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/07811 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15787 , H01L2924/16151 , H01L2924/16195 , H01L2924/16235 , H01L2924/3011 , H01L2924/3025 , H03H3/007 , H03H9/0547 , H03H9/0585 , H03H9/059 , H03H9/1057 , H03H9/1064 , H03H9/1071 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： A packaged microelectronic device is provided which includes: (a) a unit having a chip with an upwardly-facing front surface and a downwardly-facing rear surface, a lid overlying at least a portion of the front surface of the chip, the lid having a top surface facing upwardly away from the chip and unit connections exposed at the top surface of the lid. At least some of the unit connections are electrically connected to the chip. The packaged microelectronic device also includes a package structure including structure defining package terminals, at least some of the package terminals being electrically connected to the chip. The package structure, the unit or both define a downwardly-facing bottom surface of the package, the terminals being exposed at the bottom surface.

44. 发明申请

US20060099789A1 Micro lead frame packages and methods of manufacturing the same 有权
标题翻译：微型引线框架封装及其制造方法
公开(公告)号：US20060099789A1
公开(公告)日：2006-05-11
申请号：US10972180
申请日：2004-10-22
申请人： Craig Mitchell , Belgacem Haba
发明人： Craig Mitchell , Belgacem Haba
IPC分类号： H01L21/44
CPC分类号： H01L23/4951 , H01L21/565 , H01L23/3114 , H01L23/49572 , H01L24/48 , H01L2224/06135 , H01L2224/06136 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/4824 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Microelectronic packages include a microelectronic element and portions of a lead frame disposed beneath the microelectronic element. The lead frame may be laminated with a dielectric element and the resulting laminate may be punched to remove the bus bar included in the lead frame, thereby forming an in-process unit having the leads and terminals of the original lead frame attached to the dielectric element. A microelectronic element such as a semiconductor chip may be assembled with such an in-process element and, desirably, encapsulated to form a package.
摘要翻译：微电子封装包括微电子元件和设置在微电子元件下方的引线框架的部分。引线框架可以与电介质元件层压，并且可以冲压所得到的层压板以去除引线框架中包括的汇流条，从而形成工艺单元，其中原始引线框架的引线和端子附接到电介质元件。诸如半导体芯片的微电子元件可以与这样的处理元件组装，并且期望地封装以形成封装。

45. 发明授权

US06169328A Semiconductor chip assembly 有权
标题翻译：半导体芯片组装
公开(公告)号：US06169328A
公开(公告)日：2001-01-02
申请号：US09246056
申请日：1999-02-08
申请人： Craig Mitchell , Mike Warner , Jim Behlen
发明人： Craig Mitchell , Mike Warner , Jim Behlen
IPC分类号： H01L2348
CPC分类号： H01L21/56 , H01L21/563 , H01L23/49811 , H01L23/49827 , H01L23/4985 , H01L24/72 , H01L24/75 , H01L24/81 , H01L2224/16 , H01L2224/73203 , H01L2224/75 , H01L2224/81801 , H01L2224/83136 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/15311 , H01L2924/1532 , H01L2924/16152 , H01L2924/19041 , H01L2924/19043 , H05K1/118 , H05K3/361 , H05K3/4084 , H05K2201/0133 , H05K2201/0394 , H05K2201/0397 , H05K2201/09081 , H05K2201/091 , H05K2203/063 , H01L2924/00
摘要： A semiconductor chip package structure for providing a reliable interface between a semiconductor chip and a PWB to accommodate for the thermal coefficient of expansion mismatch therebetween. The interface between a chip and a PWB is comprised of a package substrate having a plurality of compliant pads defining channels therebetween. The package substrate is typically comprised of a flexible dielectric sheet that has leads and terminals on at least one surface thereof. The pads have a first coefficient of thermal expansion (“CTE”) and are comprised of a material having a fairly low modulus of elasticity. An encapsulant having a second CTE lower than the CTE of the compliant pads is disposed within the channels to form a uniform encapsulation layer. The pads are in rough alignment with the conductive terminals on the package substrate thereby allowing independent movement of the terminals during thermal cycling of the chip. The encapsulant encases the conductive leads electrically connecting the terminals to chip contacts on a face surface of the chip. The lower CTE of the encapsulant controls the flexing of the conductive leads so that the leads do not prematurely fatigue and become unreliable while the lower modulus compliant pads relieve the stress on the solder balls induced by the CTE mismatch of the chip and the PWB.
摘要翻译：一种用于在半导体芯片和PWB之间提供可靠接口的半导体芯片封装结构，以适应其间的热膨胀系数不匹配。芯片和PWB之间的接口包括具有多个在其间形成通道的柔性衬垫的封装衬底。封装基板通常由在其至少一个表面上具有引线和端子的柔性电介质片构成。垫具有第一热膨胀系数（“CTE”），并且由具有相当低的弹性模量的材料组成。具有比柔性焊盘的CTE低的第二CTE的密封剂设置在通道内以形成均匀的封装层。焊盘与封装衬底上的导电端子粗略对准，从而允许在芯片的热循环期间端子的独立移动。密封剂封装导电引线，将引线电连接到芯片的表面上的芯片触点。密封剂的较低CTE控制导电引线的弯曲，使得引线不会过早地疲劳并变得不可靠，而较低模量的柔性焊盘缓解由芯片和PWB的CTE不匹配引起的焊球上的应力。

46. 发明授权

US09125333B2 Electrical barrier layers 有权
标题翻译：电阻层
公开(公告)号：US09125333B2
公开(公告)日：2015-09-01
申请号：US13183870
申请日：2011-07-15
申请人： Cyprian Uzoh , Vage Oganesian , Ilyas Mohammed , Belgacem Haba , Piyush Savalia , Craig Mitchell
发明人： Cyprian Uzoh , Vage Oganesian , Ilyas Mohammed , Belgacem Haba , Piyush Savalia , Craig Mitchell
IPC分类号： H05K1/03 , H05K1/09 , H05K3/40
CPC分类号： H01L24/05 , H01L2224/04042 , H01L2224/05083 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05169 , H01L2224/056 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01074 , H01L2924/013 , H05K1/09 , H05K3/4007 , H05K2201/032 , H05K2201/0326 , H05K2201/0338
摘要： Barrier layers for use in electrical applications. In some embodiments the barrier layer is a laminated barrier layer. In some embodiments the barrier layer includes a graded barrier layer.
摘要翻译：用于电气应用的阻隔层。在一些实施例中，阻挡层是层压阻挡层。在一些实施例中，阻挡层包括梯度阻挡层。

47. 发明授权

US08937361B2 BSI image sensor package with variable-height silicon for even reception of different wavelengths 有权
标题翻译： BSI图像传感器封装，具有可变高度的硅，用于均匀接收不同的波长
公开(公告)号：US08937361B2
公开(公告)日：2015-01-20
申请号：US13114243
申请日：2011-05-24
申请人： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Piyush Savalia , Craig Mitchell
发明人： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Piyush Savalia , Craig Mitchell
IPC分类号： H01L31/0232 , H01L27/146
CPC分类号： H01L27/14625 , H01L27/1461 , H01L27/14629 , H01L27/14632 , H01L27/1464 , H01L27/14645 , H01L27/14687
摘要： A microelectronic image sensor assembly for backside illumination and method of making same are provided. The assembly includes a microelectronic element having contacts exposed at a front face and light sensing elements arranged to receive light of different wavelengths through a rear face. A semiconductor region has a first thickness between the first light sensing element and the rear face and a second thickness between the second light sensing element and the rear face such that the first and second light sensing elements receive light of substantially the same intensity. A dielectric region is provided at least substantially filling a space of the semiconductor region adjacent at least one of the light sensing elements. The dielectric region may include at least one light guide.
摘要翻译：提供了一种用于背面照明的微电子图像传感器组件及其制造方法。该组件包括具有在正面暴露的触点的微电子元件和被布置成通过后表面接收不同波长的光的光感测元件。半导体区域在第一光感测元件和后表面之间具有第一厚度，并且在第二光感测元件和后表面之间具有第二厚度，使得第一和第二光感测元件接收基本上相同强度的光。提供至少基本上填充与至少一个光感测元件相邻的半导体区域的空间的电介质区域。电介质区域可以包括至少一个光导。

48. 发明授权

US08916781B2 Cavities containing multi-wiring structures and devices 有权
标题翻译：包含多层结构和设备的腔
公开(公告)号：US08916781B2
公开(公告)日：2014-12-23
申请号：US13296785
申请日：2011-11-15
申请人： Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Cyprian Emeka Uzoh
发明人： Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Cyprian Emeka Uzoh
IPC分类号： H05K1/11 , H05K1/03 , H05K1/09 , H05K1/00 , H01L23/498 , H01R12/71 , H05K3/42
CPC分类号： H05K1/0271 , H01L23/49827 , H01L2924/0002 , H01R12/714 , H05K1/114 , H05K1/115 , H05K3/42 , H05K2201/09645 , H05K2201/10378 , H05K2203/0242 , H05K2203/025 , Y10T29/49165 , H01L2924/00
摘要： An interconnection component includes an element with an opening, a plurality of conductors electrically insulted from one another extending through the opening, and a plurality of second contacts electrically insulated from one another. The element is comprised of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. At least some of the conductors extend along at least one inner surface of the opening. The conductors define a plurality of wettable first contacts at the first surface. The first contacts are at least partially aligned with the opening in a direction of the thickness and electrically insulated from one another.
摘要翻译：互连部件包括具有开口的元件，延伸穿过开口彼此电绝缘的多个导体以及彼此电绝缘的多个第二触点。该元件由热膨胀系数小于10ppm /℃的材料构成。至少一些导体沿开口的至少一个内表面延伸。导体在第一表面限定多个可润湿的第一接触。第一触点在厚度方向上与开口至少部分地对齐，并且彼此电绝缘。

49. 发明授权

US08772946B2 Reduced stress TSV and interposer structures 有权
标题翻译：减少应力TSV和插入结构
公开(公告)号：US08772946B2
公开(公告)日：2014-07-08
申请号：US13492064
申请日：2012-06-08
申请人： Cyprian Emeka Uzoh , Charles G. Woychik , Terrence Caskey , Kishor V. Desai , Huailiang Wei , Craig Mitchell , Belgacem Haba
发明人： Cyprian Emeka Uzoh , Charles G. Woychik , Terrence Caskey , Kishor V. Desai , Huailiang Wei , Craig Mitchell , Belgacem Haba
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/34 , H01L21/76841 , H01L21/76883 , H01L21/76885 , H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L24/05 , H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/05558 , H01L2224/05567 , H01L2224/0557 , H01L2224/05571 , H01L2224/1134 , H01L2224/1147 , H01L2224/13082 , H01L2224/13083 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/13184 , H01L2224/13565 , H01L2224/32105 , H01L2924/00011 , H01L2924/01322 , H01L2924/07811 , H01L2924/12042 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/014 , H01L2224/81805
摘要： A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall.
摘要翻译：部件可以包括在基板的开口内延伸的基板和导电通孔。基底可以具有第一和第二相对表面。开口可以从第一表面延伸到第二表面，并且可以具有远离第一表面延伸的内壁。电介质材料可以在内壁暴露。导电通孔可以在邻近第一表面的开口内限定释放通道。释放通道可以具有在与第一表面平行且在五微米以内的平面的方向上离内壁的第一距离内的边缘，第一距离是最小宽度的一微米和百分之五的最小宽度在飞机上开了边缘可以沿着内壁延伸以跨越内壁的圆周的至少百分之五。

50. 发明授权

US08652935B2 Void-free wafer bonding using channels 有权
标题翻译：使用通道的无空隙晶片接合
公开(公告)号：US08652935B2
公开(公告)日：2014-02-18
申请号：US12970529
申请日：2010-12-16
申请人： Ilyas Mohammed , Piyush Savalia , Craig Mitchell , Vage Oganesian , Belgacem Haba
发明人： Ilyas Mohammed , Piyush Savalia , Craig Mitchell , Vage Oganesian , Belgacem Haba
IPC分类号： H01L21/30
CPC分类号： H01L23/562 , B81C1/00269 , B81C1/00357 , H01L21/2007 , H01L21/561 , H01L21/563 , H01L21/568 , H01L23/13 , H01L24/05 , H01L24/29 , H01L24/32 , H01L24/83 , H01L24/94 , H01L24/97 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L29/0657 , H01L2224/29186 , H01L2224/2919 , H01L2224/32057 , H01L2224/32145 , H01L2224/32225 , H01L2224/83051 , H01L2224/83191 , H01L2224/83345 , H01L2224/83385 , H01L2224/83855 , H01L2224/83856 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06555 , H01L2225/06575 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01033 , H01L2924/014 , H01L2924/0665 , H01L2924/10158 , H01L2924/10253 , H01L2924/1027 , H01L2924/1032 , H01L2924/1037 , H01L2924/14 , H01L2924/1461 , H01L2924/3511 , H01L2224/83 , H01L2924/00
摘要： A method of bonding first and second microelectronic elements includes pressing together a first substrate containing active circuit elements therein with a second substrate, with a flowable dielectric material between confronting surfaces of the respective substrates, each of the first and second substrates having a coefficient of thermal expansion less than 10 parts per million/° C., at least one of the confronting surfaces having a plurality of channels extending from an edge of such surface, such that the dielectric material between planes defined by the confronting surfaces is at least substantially free of voids and has a thickness over one micron, and at least some of the dielectric material flows into at least some of the channels.
摘要翻译：接合第一和第二微电子元件的方法包括将含有有源电路元件的第一衬底与第二衬底压在一起，在相应衬底的相对表面之间具有可流动介电材料，第一和第二衬底中的每一个具有热系数膨胀小于10ppm /℃，至少一个相对表面具有从该表面的边缘延伸的多个通道，使得由相对表面限定的平面之间的电介质材料至少基本上不含空隙并且具有超过一微米的厚度，并且至少一些介电材料流入至少一些通道。

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