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41. 发明申请

US20110128777A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110128777A1
公开(公告)日：2011-06-02
申请号：US12952609
申请日：2010-11-23
申请人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
IPC分类号： G11C11/24 , H01L29/12 , G11C7/00
CPC分类号： G11C11/405 , G11C16/0425 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11521 , H01L27/11551 , H01L27/1156 , H01L27/1203 , H01L27/1225
摘要： The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is formed on or in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.
摘要翻译：半导体器件包括第一布线; 第二布线第三线; 第四布线具有第一栅电极，第一源电极和第一漏电极的第一晶体管; 以及具有第二栅电极，第二源电极和第二漏电极的第二晶体管。第一晶体管形成在包括半导体材料的衬底上或衬底中。第二晶体管包括氧化物半导体层。

42. 发明申请

US20110121286A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110121286A1
公开(公告)日：2011-05-26
申请号：US12949641
申请日：2010-11-18
申请人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
IPC分类号： H01L27/092
CPC分类号： H01L21/02554 , G11C11/403 , G11C11/405 , G11C16/0425 , H01L21/02565 , H01L21/02631 , H01L21/02664 , H01L27/0688 , H01L27/105 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/1156 , H01L27/1203 , H01L27/1225
摘要： It is an object to provide a semiconductor device with a novel structure. The semiconductor device includes memory cells connected to each other in series and a capacitor. One of the memory cells includes a first transistor connected to a bit line and a source line, a second transistor connected to a signal line and a word line, and a capacitor connected to the word line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor are connected to one another.
摘要翻译：本发明的目的是提供一种具有新颖结构的半导体器件。半导体器件包括彼此串联连接的存储单元和电容器。一个存储单元包括连接到位线和源极线的第一晶体管，连接到信号线和字线的第二晶体管，以及连接到字线的电容器。第二晶体管包括氧化物半导体层。第一晶体管的栅电极，第二晶体管的源电极和漏电极之一以及电容器的一个电极彼此连接。

43. 发明申请

US20110116310A1 SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF 有权
标题翻译：半导体器件及其驱动方法
公开(公告)号：US20110116310A1
公开(公告)日：2011-05-19
申请号：US12945476
申请日：2010-11-12
申请人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
IPC分类号： G11C11/4096
CPC分类号： G11C7/062 , G11C7/067 , G11C11/40 , G11C2207/005 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L27/0688 , H01L27/105 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/1156 , H01L27/1203 , H01L27/1225 , H01L29/155 , H01L29/205
摘要： A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which drives a plurality of second signal lines and a plurality of word lines so as to select the memory cell specified by an address signal; a potential generating circuit which generates a writing potential and a plurality of reading potentials to supply to a writing circuit and a reading circuit; and a control circuit which selects one of a plurality of voltages for correction on a basis of results of the reading circuit comparing a potential of the bit line with the plurality of reading potentials.
摘要翻译：半导体器件包括：源极线; 有点线字线连接到位线和字线的存储单元; 驱动电路，其驱动多个第二信号线和多个字线，以选择由地址信号指定的存储单元; 产生写入电位和多个读取电位以供应到写入电路和读取电路的电位产生电路; 以及控制电路，其基于将所述位线的电位与所述多个读取电位进行比较的所述读取电路的结果来选择用于校正的多个电压中的一个。

44. 发明申请

US20110089955A1 Element Substrate, Inspecting Method, and Manufacturing Method of Semiconductor Device 有权
标题翻译：元件基板，检测方法和半导体器件的制造方法
公开(公告)号：US20110089955A1
公开(公告)日：2011-04-21
申请号：US12910426
申请日：2010-10-22
申请人： Kiyoshi Kato , Konami Izumi , Masahiko Hayakawa , Koichiro Kamata
发明人： Kiyoshi Kato , Konami Izumi , Masahiko Hayakawa , Koichiro Kamata
IPC分类号： G01R27/04
CPC分类号： G01R31/2822 , G01R31/2886 , G01R31/3025 , H01L27/13
摘要： A substrate including a semiconductor layer, where characteristics of an element can be evaluated with high reliability, and an evaluating method thereof are provided. A substrate including a semiconductor layer of the invention has a closed-loop circuit in which an antenna coil and a semiconductor element are connected in series, and a surface of an area over which the circuit is formed is covered with an insulating film. By using such a circuit, a contactless inspection can be carried out. Further, a ring oscillator can be substituted for the closed-loop circuit.
摘要翻译：提供了包括可以以高可靠性评估元件的特性的半导体层的基板及其评价方法。包括本发明的半导体层的衬底具有一个闭环电路，其中天线线圈和半导体元件串联连接，并且形成有电路的区域的表面被绝缘膜覆盖。通过使用这样的电路，可以进行非接触检查。此外，环形振荡器可以代替闭环电路。

45. 发明授权

US07923719B2 Semiconductor memory device wherein wiring contact is made through an opening in an organic compound layer 有权
标题翻译：半导体存储器件，其中通过有机化合物层中的开口制造布线接触
公开(公告)号：US07923719B2
公开(公告)日：2011-04-12
申请号：US11790348
申请日：2007-04-25
申请人： Shunpei Yamazaki , Kiyoshi Kato , Ryoji Nomura
发明人： Shunpei Yamazaki , Kiyoshi Kato , Ryoji Nomura
IPC分类号： H01L29/08 , H01L51/40 , H01L21/8242
CPC分类号： H01L27/12 , B82Y10/00 , G11C13/0014 , G11C13/004 , G11C2013/0054 , H01L27/1248 , H01L27/13 , H01L27/285
摘要： In the present invention, a semiconductor device that has a nonvolatile memory element to which data can be written at times other than during manufacture and in which forgery and the like performed by rewriting of data can be prevented is provided. In addition, a semiconductor device in which a high level of integration is possible is provided. Furthermore, a semiconductor device in which miniaturization is possible is provided. In a semiconductor device having a memory element that includes a first conductive layer, a second conductive layer, and an organic compound layer interposed between the first conductive layer and the second conductive layer; the second conductive layer is connected to a wiring, formed in the same way as the first conductive layer is formed, through an opening formed in the organic compound layer.
摘要翻译：在本发明中，提供了一种具有非易失性存储元件的半导体器件，可以防止在制造过程中可以写入数据的非易失性存储元件，并且可以防止通过重写数据进行伪造等。此外，提供了其中可以实现高集成度的半导体器件。此外，提供了可以进行小型化的半导体器件。在具有包含第一导电层，第二导电层和介于第一导电层和第二导电层之间的有机化合物层的存储元件的半导体器件中; 第二导电层通过形成在有机化合物层中的开口连接到与形成第一导电层的方式相同的布线。

46. 发明授权

US07858985B2 Integrated circuit, semiconductor device comprising the same, electronic device having the same, and driving method of the same 有权
标题翻译：集成电路，包括该集成电路的半导体器件，具有该集成电路的电子器件及其驱动方法
公开(公告)号：US07858985B2
公开(公告)日：2010-12-28
申请号：US12474766
申请日：2009-05-29
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： H01L29/76
CPC分类号： H01L27/108 , G11C11/404 , H01L27/12 , H01L29/7841 , H01L29/78621 , H01L29/78648
摘要： An integrated circuit mounting a DRAM which can realize high integration without complicated manufacturing steps. The integrated circuit according to the invention comprises a DRAM in which a plurality of memory cells each having a thin film transistor are disposed. The thin film transistor comprises an active layer including a channel forming region, and first and second electrodes overlapping with each other with the channel forming region interposed therebetween. By controlling a drain voltage of the thin film transistor according to data, it is determined whether to accumulate holes in the channel forming region or not, and data is read out by confirming whether or not holes are accumulated.
摘要翻译：一种安装DRAM的集成电路，可以实现高集成度，而无需复杂的制造步骤。根据本发明的集成电路包括其中设置有各自具有薄膜晶体管的多个存储单元的DRAM。薄膜晶体管包括有沟槽形成区域的有源层，并且第一和第二电极彼此重叠，沟道形成区域插入其间。通过根据数据控制薄膜晶体管的漏极电压，确定是否在沟道形成区域中积累空穴，并且通过确认孔是否被累积来读出数据。

47. 发明授权

US07842561B2 Semiconductor integrated circuit, semiconductor device, and manufacturing method of the semiconductor integrated circuit 有权
标题翻译：半导体集成电路，半导体器件和半导体集成电路的制造方法
公开(公告)号：US07842561B2
公开(公告)日：2010-11-30
申请号：US12222081
申请日：2008-08-01
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： H01L21/84
CPC分类号： H01L27/112 , H01L21/76892 , H01L21/76894 , H01L21/76895 , H01L27/0207 , H01L27/105 , H01L27/11253 , H01L27/11293 , H01L27/12 , H01L27/1266 , H01L27/1285 , H01L27/1292 , H01L27/13 , H01L29/78624 , H01L2924/0002 , H01L2924/00
摘要： A chip with increased impact resistance, attractive design and reduced cost, and a manufacturing method thereof are provided. A semiconductor integrated circuit is formed on a large glass substrate, and a part of data of a ROM included therein is determined by an ink jet method or a laser cutting method. Accordingly, the cost can be reduced without requiring a photomask, resulting in an inexpensive ID chip. Further, depending on the application, the semiconductor integrated circuit is transposed to a flexible substrate, thereby an ID chip with improved impact resistance and more attractive design can be achieved.
摘要翻译：提供了具有增加的耐冲击性，有吸引力的设计和降低成本的芯片及其制造方法。半导体集成电路形成在大的玻璃基板上，其中包含的ROM的一部分数据通过喷墨法或激光切割方法来确定。因此，可以降低成本，而不需要光掩模，导致廉价的ID芯片。此外，根据应用，半导体集成电路被转置到柔性基板，从而可以实现具有改善的耐冲击性和更有吸引力的设计的ID芯片。

48. 发明申请

US20100231100A1 Cooling storage cabinet 审中-公开
标题翻译：冷却储藏柜
公开(公告)号：US20100231100A1
公开(公告)日：2010-09-16
申请号：US12308458
申请日：2007-06-14
申请人： Kiyoshi Kato , Etsuo Sugiyama , Masayuki Nishio , Daisuke Hiraki
发明人： Kiyoshi Kato , Etsuo Sugiyama , Masayuki Nishio , Daisuke Hiraki
IPC分类号： F25D23/00
CPC分类号： F25D21/14 , F25D2321/146
摘要： The present invention can include a cooling storage cabinet including a storage cabinet body having a side face, a drain head for draining water to the outside, the drain head protruding from the side face of the storage cabinet body, a vaporizing receptacle for collecting water from the drain pipe, the vaporizing receptacle being disposed below the drain head and having a face opposed to the side face of the storage cabinet body, and a heater for vaporizing the drained water. The vaporizing receptacle can includes a concavity formed on the face, the concavity being configured to form a layer of air between the side face of the storage cabinet body.
摘要翻译：本发明可以包括一个冷却储藏柜，它包括一个具有侧面的储存箱主体，用于向外部排水的排水头，从储藏箱主体的侧面突出的排水头，一个用于从排水管，蒸发容器设置在排水头下方并具有与储藏箱主体的侧面相对的面，以及用于蒸发排水的加热器。蒸发容器可以包括形成在表面上的凹部，该凹部构造成在储藏箱主体的侧面之间形成空气层。

49. 发明授权

US07714633B2 Limiter and semiconductor device using the same 有权
标题翻译：限制器和半导体器件使用相同
公开(公告)号：US07714633B2
公开(公告)日：2010-05-11
申请号：US10593577
申请日：2005-04-06
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： H03K5/00 , H01L23/62
CPC分类号： H01L27/1266 , G06K19/07735 , G06K19/07749 , H01L23/49855 , H01L27/0266 , H01L27/12 , H01L27/1214 , H01L27/13 , H01L2924/0002 , H01L2924/09701 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
摘要： By using a stacked gate transistor including a floating gate in a limiter, a threshold voltage Vth of the stacked gate transistor can be corrected by controlling the amount of charge accumulated in the floating gate of the stacked gate transistor even in the case where there are variations in the threshold voltage Vth of the stacked gate transistor.
摘要翻译：通过在限幅器中使用包括浮置栅极的层叠栅极晶体管，可以通过控制堆叠栅极晶体管的浮置栅极中累积的电荷量来校正层叠栅极晶体管的阈值电压Vth，即使在存在变化的情况下在层叠栅极晶体管的阈值电压Vth中。

50. 发明申请

US20100057660A1 OPERATION MANAGEMENT DEVICE, OPERATION MANAGEMENT METHOD, AND OPERATION MANAGEMENT PROGRAM 有权
标题翻译：操作管理设备，操作管理方法和操作管理程序
公开(公告)号：US20100057660A1
公开(公告)日：2010-03-04
申请号：US12530762
申请日：2008-03-04
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： G06N5/02
CPC分类号： H04L41/0604 , G06F11/008 , G06F11/3452 , G06F2201/86 , H04L41/147
摘要： An operation management apparatus decides that newly-generated event data and previously-existing predictive event data match if the attribute values of the event data match the attribute values of the predictive event data excluding reference values. In such a case, the apparatus identifies individual filter information whose attribute values excluding reference values match the attribute values of the event data, and substitutes the attribute values of the event data for variables in each piece of individual filter information belonging to a group to which the individual filter information belongs, thereby generating predictive event data for each piece of individual filter information. The apparatus decides whether or not each piece of event data that is associated in a predictive event index with the group to which the individual filter information that matches the event data used for generating the predictive event data belongs satisfies the individual filter information of operation rule information corresponding to the group, and if satisfies, performs processing defined by the operation rule information.
摘要翻译：如果事件数据的属性值与除了参考值的预测事件数据的属性值相匹配，则操作管理装置判定新生成的事件数据和先前存在的预测事件数据相匹配。在这种情况下，该装置识别除了参考值的属性值与事件数据的属性值相匹配的单个过滤器信息，并且将属于其的每个单独过滤器信息中的变量的事件数据的属性值替换为各个过滤器信息属于，从而为每个单独的过滤器信息生成预测事件数据。该装置判定与预测事件索引相关联的每条事件数据是否与与用于生成预测事件数据的事件数据匹配的各个过滤器信息所对应的组满足操作规则信息的各个过滤器信息对应于组，并且如果满足，则执行由操作规则信息定义的处理。

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