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41. 发明授权

US07890071B2 Handheld audio system 有权
标题翻译：手持音响系统
公开(公告)号：US07890071B2
公开(公告)日：2011-02-15
申请号：US11126554
申请日：2005-05-11
申请人： Michael R. May , Marcus W. May , Dave Baker , Matthew Brady Henson
发明人： Michael R. May , Marcus W. May , Dave Baker , Matthew Brady Henson
IPC分类号： H04B1/38
CPC分类号： H04H40/45
摘要： A handheld audio system includes a radio signal decoder integrated circuit (IC) and a digital audio processing integrated circuit. The radio signal decoder integrated circuit produces a digital left channel signal and a digital right channel signal from a received radio signal in accordance with an enable signal and also produces a system clock. The digital audio processing integrated circuit includes a DC-to-DC converter and a processing module. The DC-to-DC converter is operably coupled to produce at least one power supply voltage based on the system clock. The processing module is operably coupled to produce the enable signal when the at least one power supply voltage has reached a desired level and to produce audio signals for audio playback from at least one of the digital left and right channel signals and a stored digital audio file.
摘要翻译：手持音频系统包括无线电信号解码器集成电路（IC）和数字音频处理集成电路。无线电信号解码器集成电路根据使能信号从接收的无线电信号产生数字左声道信号和数字右声道信号，并且还产生系统时钟。数字音频处理集成电路包括DC-DC转换器和处理模块。 DC-DC转换器可操作地耦合以基于系统时钟产生至少一个电源电压。当至少一个电源电压已经达到期望的水平并且从数字左声道信号和右声道信号中的至少一个产生用于音频回放的音频信号时，处理模块可操作地耦合以产生使能信号，并且存储的数字音频文件。

42. 发明授权

US07620380B2 Adjustable automatic gain control 失效
标题翻译：可调自动增益控制
公开(公告)号：US07620380B2
公开(公告)日：2009-11-17
申请号：US11388795
申请日：2006-03-24
申请人： Jon David Hendrix , Michael R. May
发明人： Jon David Hendrix , Michael R. May
IPC分类号： H04B1/06
CPC分类号： H04B1/28
摘要： A method for adjusting automatic gain control (AGC) of a radio receiver begins when a primary AGC module establishes an AGC setting for the radio receiver to produce a primary AGC setting. The method continues when a supervisory AGC module compares performance of the radio receiver utilizing the primary AGC setting with a plurality of performance thresholds. The method continues with the supervisory AGC module adjusting the primary AGC setting to produce adjusted AGC setting when the performance of the radio receiver utilizing the primary AGC setting compares unfavorable with a first performance threshold of the plurality of performance thresholds. The method continues with the supervisory AGC module overwriting the primary AGC setting with alternative AGC setting when the performance of the radio receiver utilizing the primary AGC setting compares unfavorable with a second performance threshold of the plurality of performance thresholds.
摘要翻译：一种用于调整无线电接收机的自动增益控制（AGC）的方法，当主AGC模块建立无线电接收机的AGC设置以产生主AGC设置时，开始。当监控AGC模块使用主AGC设置与多个性能阈值比较无线电接收机的性能时，继续该方法。当使用主AGC设置的无线电接收机的性能与多个性能阈值的第一性能阈值不利时相比较时，继续监视AGC模块调整主AGC设置以产生调整的AGC设置。当使用主AGC设置的无线电接收机的性能与多个性能阈值的第二性能阈值相比较时，该方法继续，监控AGC模块用替代的AGC设置覆盖主AGC设置。

43. 发明授权

US07599451B2 Sample rate conversion module and applications thereof 失效
标题翻译：采样率转换模块及其应用
公开(公告)号：US07599451B2
公开(公告)日：2009-10-06
申请号：US11126832
申请日：2005-05-11
申请人： Michael R. May
发明人： Michael R. May
IPC分类号： H04L27/06 , H03M7/00
CPC分类号： H04L25/05 , H03H17/0286 , H03H17/0614 , H03H17/0621 , H04L27/142 , H04L2027/0024 , H04L2027/0087
摘要： A sample rate converter includes an upsampling module, a low pass filter, and a linear sample rate conversion module. The upsampling module is operably coupled up-sample a digital input signal having a first rate to produce a digitally up-sampled signal. The low pass filter is operably coupled to low pass filter the digitally up-sampled signal to produce a digitally filtered signal at an up-sampled rate. The linear sample rate conversion module is operably coupled to convert the digitally up-sampled signal into a sample rate adjusted digital signal having a second rate based on an control feedback signal and a linear function, wherein a relationship between the first rate and the second rate is a non-power of two.
摘要翻译：采样率转换器包括上采样模块，低通滤波器和线性采样率转换模块。上采样模块可操作地耦合上采样具有第一速率的数字输入信号以产生数字上采样信号。低通滤波器可操作地耦合到低通滤波器的数字上采样信号，以产生以上采样速率的数字滤波信号。线性采样率转换模块可操作地耦合以将数字上采样信号转换为基于控制反馈信号和线性函数的具有第二速率的采样率调整数字信号，其中第一速率与第二速率之间的关系是一个没有力量的两个。

44. 发明授权

US07515078B2 Programmable sample rate analog to digital converter and method for use therewith 有权
标题翻译：可编程采样率模数转换器及其使用方法
公开(公告)号：US07515078B2
公开(公告)日：2009-04-07
申请号：US11728812
申请日：2007-03-26
申请人： Michael R. May
发明人： Michael R. May
IPC分类号： H03M3/00
CPC分类号： H03H17/0671 , H03M3/454 , H03M3/498
摘要： A programmable sample rate ADC includes a delta sigma modulator for producing a digital signal, and a programmable decimation filter, that includes X stages of integration, a down-sampling stage for down-sampling by a factor of N, and Y stages of differentiation. The programmable sample rate ADC produces a digital output signal at a substantially constant frequency.
摘要翻译：可编程采样率ADC包括用于产生数字信号的Δ-Σ调制器和可编程抽取滤波器，其包括X级积分，用于以N因子进行下采样的下采样级和Y级差分。可编程采样率ADC以基本恒定的频率产生数字输出信号。

45. 发明申请

US20090085620A1 CLOCK SYSTEM AND APPLICATIONS THEREOF 有权
标题翻译：时钟系统及其应用
公开(公告)号：US20090085620A1
公开(公告)日：2009-04-02
申请号：US11862312
申请日：2007-09-27
申请人： Michael R. May , Raymond L. Vargas
发明人： Michael R. May , Raymond L. Vargas
IPC分类号： H03L7/06
CPC分类号： H03L7/0995 , G06F1/06
摘要： A clock system includes a phase locked loop, a phase divider, and a control module. The phase locked loop (PLL) produces a plurality of phase-offset output oscillations. The phase divider generates a clock signal from one or more of the plurality of phase-offset output oscillations based on a phase divider control signal. The control module generates the phase divider control signal based on a desired setting for the clock signal.
摘要翻译：时钟系统包括锁相环，相位分配器和控制模块。锁相环（PLL）产生多个相位偏移输出振荡。相位分离器基于相位分配器控制信号从多个相位偏移输出振荡中的一个或多个产生时钟信号。控制模块基于时钟信号的期望设置产生相位分配器控制信号。

46. 发明申请

US20070279027A1 Semiconductor device and system and method of crystal sharing 有权
标题翻译：半导体器件及晶体共享系统及方法
公开(公告)号：US20070279027A1
公开(公告)日：2007-12-06
申请号：US11446612
申请日：2006-06-05
申请人： Michael R. May , Marcus William May
发明人： Michael R. May , Marcus William May
IPC分类号： G05F1/00
CPC分类号： H02M1/084
摘要： A system includes a first semiconductor device, a second semiconductor device, and an external crystal oscillator. The first semiconductor device includes a source voltage output and an external pin input. The first semiconductor device includes a direct current-to-direct current (DC-DC) converter circuit that provides the source voltage output. The second semiconductor device includes a source voltage input that is coupled to the source voltage output of the first semiconductor device and includes a clock signal output. The external crystal oscillator is coupled via an input of the second semiconductor device to a first oscillator clock generation circuit.
摘要翻译：一种系统包括第一半导体器件，第二半导体器件和外部晶体振荡器。第一半导体器件包括源极电压输出和外部引脚输入。第一半导体器件包括提供源极电压输出的直流 - 直流（DC-DC）转换器电路。第二半导体器件包括耦合到第一半导体器件的源极电压输出并包括时钟信号输出的源极电压输入。外部晶体振荡器经由第二半导体器件的输入耦合到第一振荡器时钟产生电路。

47. 发明授权

US07245247B1 Analog to digital signal converter having sampling circuit with divided integrating capacitance 失效
标题翻译：模数转换器具有分频积分电容的采样电路
公开(公告)号：US07245247B1
公开(公告)日：2007-07-17
申请号：US11355934
申请日：2006-02-16
申请人： Michael R. May , Matthew D. Felder
发明人： Michael R. May , Matthew D. Felder
IPC分类号： H03M3/00
CPC分类号： H03M3/496 , G11C27/024 , H03M3/454
摘要： An analog-to-digital converter (ADC) includes a modulator and a decimation filter. The modulator includes a sampling circuit, integrator, a quantizer, and feedback circuitry. The sampling circuit includes at least one sampling capacitor and a plurality of dump capacitors. A sum of the capacitance of the dump capacitors is substantially equal to a capacitance of the sampling capacitors. Combined sampling/dump capacitors having approximately equal capacitance may be used with the sampling circuit.
摘要翻译：模数转换器（ADC）包括调制器和抽取滤波器。调制器包括采样电路，积分器，量化器和反馈电路。采样电路包括至少一个采样电容器和多个转储电容器。转储电容器的电容之和基本上等于采样电容器的电容。采样电路可以使用具有大致相等电容的组合采样/去电容器。

48. 发明授权

US07227478B1 Sample rate converter with selectable sampling rate and timing reference 有权
标题翻译：采样率转换器，可选择采样率和定时参考
公开(公告)号：US07227478B1
公开(公告)日：2007-06-05
申请号：US11302761
申请日：2005-12-14
申请人： Jon David Hendrix , Michael R. May
发明人： Jon David Hendrix , Michael R. May
IPC分类号： H03M7/00
CPC分类号： H03H17/0628
摘要： A sample rate converter includes an up-conversion module, a linear interpolator module, and a parameter control module. The up-conversion module is operable to convert a first data rate to a second data rate of a data signal. The linear interpolator module is operable to receive the data signal at the second data rate and to produce therefrom a data signal at a desired rate based on at least one parameter. The parameter control module is operable to produce the at least one parameter based on the desired rate.
摘要翻译：采样率转换器包括上转换模块，线性内插器模块和参数控制模块。上变换模块可操作以将第一数据速率转换为数据信号的第二数据速率。线性内插器模块可操作以基于第二数据速率接收数据信号，并且基于至少一个参数以期望的速率从其产生数据信号。参数控制模块可操作以基于期望速率产生至少一个参数。

49. 发明授权

US06633187B1 Method and apparatus for enabling a stand alone integrated circuit 有权
标题翻译：用于实现独立集成电路的方法和装置
公开(公告)号：US06633187B1
公开(公告)日：2003-10-14
申请号：US09716731
申请日：2000-11-20
申请人： Michael R. May , Marcus W. May
发明人： Michael R. May , Marcus W. May
IPC分类号： H03K302
CPC分类号： G06F1/24 , H03K17/223
摘要： A method and apparatus for enabling a stand-alone integrated circuit (IC) includes processing that begins by establishing an idle state that holds at least a portion of the stand-alone integrated circuit in a reset condition when a power source is operably coupled to the stand-alone integrated circuit. A stand-alone integrated circuit includes generally an on-chip power converter, a reset circuit and some functional circuitry, which may be a microprocessor, digital signal processor digital circuitry, state machine, logic circuitry, analog circuitry, and/or any type of components and/or circuits that perform a desired electrical function. When a power enable signal is received, the on-chip power converter is enabled to generate at least 1 supply from the power source. The processing continues by enabling functionality of the stand-alone integrated circuit when the at least one supply has substantially reached a steady state condition.
摘要翻译：一种用于使得独立集成电路（IC）能够实现的方法和装置包括当电源可操作地耦合到所述独立集成电路（IC）时，通过建立将独立集成电路的至少一部分保持在复位状态的空闲状态开始的处理独立集成电路。独立集成电路通常包括片上功率转换器，复位电路和一些功能电路，其可以是微处理器，数字信号处理器数字电路，状态机，逻辑电路，模拟电路和/或任何类型的执行所需电功能的组件和/或电路。当接收到功率使能信号时，芯片上的功率转换器能够从电源产生至少1个电源。当至少一个电源基本上达到稳定状态时，继续执行独立集成电路的功能。

50. 发明授权

US06567027B2 Method and apparatus for analog to digital conversion utilizing a moving sum 有权
公开(公告)号：US06567027B2
公开(公告)日：2003-05-20
申请号：US09779810
申请日：2001-02-08
申请人： Michael R. May
发明人： Michael R. May
IPC分类号： H03M700
CPC分类号： H03H17/0621 , H03M3/418 , H03M3/462
摘要： A method and apparatus for analog to digital conversion includes processing that begins by quantizing an analog input signal to produce a stream of digital data at an over sampling rate. The processing continues by producing partially filtered data based on a moving sum of the stream of data. The processing continues by decimation filtering the partially filtered data to produce a digital output value.

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