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41. 发明申请

US20090045526A1 Stacked memory without unbalanced temperature distributions 有权
标题翻译：堆积的内存，没有不平衡的温度分布
公开(公告)号：US20090045526A1
公开(公告)日：2009-02-19
申请号：US12219429
申请日：2008-07-22
申请人： Hiroaki Ikeda
发明人： Hiroaki Ikeda
IPC分类号： H01L23/52
CPC分类号： G11C5/02 , G11C5/143 , H01L25/0657 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/0002 , H01L2924/00
摘要： A stacked memory without unbalanced temperature distributions is disclosed. According to one aspect of the invention, a through electrode in each layer is connected one after the other such that regions to be activated in neighboring layers do not overlap in a vertical direction. According to another aspect of the invention, each layer comprises an activation region distribution circuit for outputting an activation signal to, among the regions of the layer, a region having an address different from an address of a region to be activated in a layer adjacent to the layer in question.
摘要翻译：公开了一种没有不平衡温度分布的堆叠式存储器。根据本发明的一个方面，每个层中的贯通电极一个接一个地连接，使得相邻层中被激活的区域在垂直方向上不重叠。根据本发明的另一方面，每个层包括激活区域分配电路，用于在层的区域之间输出激活信号，该区域具有不同于与邻近区域中的要被激活的区域的地址不同的地址有问题的层

42. 发明申请

US20080273907A1 Positional-deviation correction apparatus, method of controlling positional deviation, and image forming apparatus 有权
标题翻译：位置偏差校正装置，位置偏差控制方法和图像形成装置
公开(公告)号：US20080273907A1
公开(公告)日：2008-11-06
申请号：US11812584
申请日：2007-06-20
申请人： Hiroaki Ikeda
发明人： Hiroaki Ikeda
IPC分类号： G03G15/00
CPC分类号： H04N1/506 , G03G15/0131 , G03G15/0194 , G03G2215/0119 , G03G2215/0141 , G03G2215/0161
摘要： A first correction pattern and a second correction pattern are formed on an endless conveyor belt. The first correction pattern is located ahead of the second correction pattern on the conveyor belt with respect to the direction of movement of the conveyor belt. A sensor detects positional information of the correction patterns. A timing changing unit (controlling unit) changes a detection timing of the second correction pattern from a time point at which the sensor detects the second correction pattern.
摘要翻译：第一校正图案和第二校正图案形成在环形传送带上。相对于传送带的移动方向，第一校正图案位于传送带上的第二校正图案的前方。传感器检测校正图案的位置信息。定时改变单元（控制单元）从传感器检测到第二校正图案的时间点改变第二校正图案的检测定时。

43. 发明授权

US07327590B2 Memory module and memory system 有权
标题翻译：内存模块和内存系统
公开(公告)号：US07327590B2
公开(公告)日：2008-02-05
申请号：US11492981
申请日：2006-07-26
申请人： Yoshinori Matsui , Toshio Sugano , Hiroaki Ikeda
发明人： Yoshinori Matsui , Toshio Sugano , Hiroaki Ikeda
IPC分类号： G11C5/02
CPC分类号： G11C11/408 , G11C5/00 , G11C5/04 , G11C5/06 , G11C7/1051 , G11C7/1063 , G11C8/12 , G11C29/1201 , G11C29/26 , G11C29/48 , H01L23/5384 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2224/0401
摘要： In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.
摘要翻译：在包括以预定数据宽度和传送速率发送/接收系统数据信号的多个DRAM芯片的存储器模块中，并且发送/接收具有较大数据宽度和较低传送速率的内部数据信号与系统数据信号，系统数据信号的传输速率受到限制。构成存储器模块的DRAM的电流消耗大，阻碍速度增加。对于该存储器模块，多个DRAM芯片堆叠在IO芯片上。每个DRAM芯片通过贯通电极连接到IO芯片，并且包括用于通过IO芯片相互转换每个DRAM芯片中的系统数据信号和内部数据信号的结构。因此，可以缩短DRAM芯片之间的布线，并且可以仅在IO芯片上设置具有大电流消耗的DLL。

44. 发明授权

US07281394B2 Method of manufacturing glass substrate and method of manufacturing information recording medium 有权
标题翻译：制造玻璃基板的方法和制造信息记录介质的方法
公开(公告)号：US07281394B2
公开(公告)日：2007-10-16
申请号：US10337865
申请日：2003-01-08
申请人： Hiroaki Ikeda , Masaru Suzuki , Kazuna Sasaki , Yumi Mukai , Jun Ozawa
发明人： Hiroaki Ikeda , Masaru Suzuki , Kazuna Sasaki , Yumi Mukai , Jun Ozawa
IPC分类号： C03C15/00 , G11B5/00
CPC分类号： C03C21/002 , B01D46/543 , C03C17/23 , C03C17/38 , C03C19/00 , C03C21/001 , C03C2218/154 , C03C2218/31 , C03C2218/365 , G11B7/2531 , G11B7/26
摘要： In a method of manufacturing a glass substrate for an information recording medium including a step for chemically strengthening the glass substrate by contacting the glass substrate with chemical strengthening processing liquid containing chemical strengthening salt, concentration of Fe and Cr is 500 ppb or less in said chemical strengthening salt, respectively. The concentration may be detected by the use of an ICP (Inductively Coupled Plasma) emission spectrometry analyzing method or a fluorescent X-ray spectroscopy analyzing method.
摘要翻译：在制造用于信息记录介质的玻璃基板的方法中，包括通过使玻璃基板与含有化学强化盐的化学强化处理液接触来化学强化玻璃基板的步骤，在所述化学品中Fe和Cr的浓度为500ppb以下分别加强盐。可以通过使用ICP（电感耦合等离子体）发射光谱分析法或荧光X射线光谱分析法来检测浓度。

45. 发明申请

US20070181991A1 Stacked semiconductor device 有权
标题翻译：堆叠半导体器件
公开(公告)号：US20070181991A1
公开(公告)日：2007-08-09
申请号：US11651517
申请日：2007-01-10
申请人： Masakazu Ishino , Hiroaki Ikeda , Junji Yamada
发明人： Masakazu Ishino , Hiroaki Ikeda , Junji Yamada
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/05573 , H01L2224/05647 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/48091 , H01L2224/48227 , H01L2224/48464 , H01L2224/48465 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06555 , H01L2225/06572 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/19107 , H01L2924/00014 , H01L2924/00
摘要： A stacked semiconductor device includes an interposer substrate having external power supply terminals, and semiconductor chips stacked on the interposer substrate. A power supply wiring arranged in the semiconductor chip located in the bottom layer is connected to the external power supply terminal via a bump electrode, the power supply wiring arranged in the semiconductor chip located in the top layer is connected to the external power supply terminal via a bonding wire, and the power supply wirings each arranged in adjacent semiconductor chips are mutually connected via the through electrode. Such a loop structure can solve a problem such that the higher the semiconductor chip, the larger its voltage drop.
摘要翻译：叠层半导体器件包括具有外部电源端子的内插基板和堆叠在插入器基板上的半导体芯片。布置在位于底层的半导体芯片中的电源布线通过凸块电极连接到外部电源端子，布置在位于顶层的半导体芯片中的电源布线通过外部电源端子经由接合线，并且各自布置在相邻的半导体芯片中的电源布线经由通孔相互连接。这种环路结构可以解决半导体芯片越高电压下降的问题。

46. 发明申请

US20070177912A1 Image formation apparatus, an image formation method, an image formation program, and a computer-readable recording medium 有权
标题翻译：图像形成装置，图像形成方法，图像形成程序和计算机可读记录介质
公开(公告)号：US20070177912A1
公开(公告)日：2007-08-02
申请号：US11699035
申请日：2007-01-29
申请人： Hiroaki Ikeda
发明人： Hiroaki Ikeda
IPC分类号： G03G15/01
CPC分类号： G03G15/0131 , G03G2215/0161
摘要： An image formation apparatus is disclosed, in which two or more toner images in different colors are superposed on an endless conveyance belt to form a color image for imprinting, and the color image for imprinting is imprinted to an imprinting medium. The image formation apparatus includes:an image formation unit for forming plural sets of marks for position error compensation for compensating for a position error of the different colors, which position error is generated when forming the color image on the conveyance belt;a detection unit for detecting position information about positions of the sets of marks for position error compensation formed on the conveyance belt by the image formation unit; anda control unit for performing a position error compensation process based on the position information detected by the detection unit.The control unit determines the number of detected positions of the marks for position error compensation from the position information for each of the sets, and performs the position error compensation process based on the position information of the marks for position error compensation of a set, the number of detected positions of which set is equal to a predetermined number out of all the sets of the marks for position error compensation.
摘要翻译：公开了一种图像形成装置，其中将不同颜色的两个或更多个调色剂图像叠加在环形传送带上以形成用于印记的彩色图像，并且用于印记的彩色图像被印刷到压印介质上。图像形成装置包括：图像形成单元，用于形成用于位置误差补偿的多组标记，用于补偿不同颜色的位置误差，当在输送带上形成彩色图像时产生位置误差; 检测单元，用于检测由所述图像形成单元在所述输送带上形成的用于位置误差补偿的标记组的位置的位置信息; 以及控制单元，用于基于由检测单元检测的位置信息执行位置误差补偿处理。控制单元根据各组的位置信息来决定用于位置误差补偿的标记的检测位置的数量，并且基于位置误差补偿的标记的位置信息进行位置误差补偿处理，所设定的检测位置的数量等于位置误差补偿的所有标记集合中的预定数量。

47. 发明申请

US20070132085A1 Stacked semiconductor device 有权
标题翻译：堆叠半导体器件
公开(公告)号：US20070132085A1
公开(公告)日：2007-06-14
申请号：US11635500
申请日：2006-12-08
申请人： Kayoko Shibata , Hiroaki Ikeda , Yoshihiko Inoue , Hitoshi Miwa , Tatsuya Ijima
发明人： Kayoko Shibata , Hiroaki Ikeda , Yoshihiko Inoue , Hitoshi Miwa , Tatsuya Ijima
IPC分类号： H01L23/02
CPC分类号： H01L25/18 , G11C5/04 , G11C29/02 , G11C29/022 , G11C29/70 , H01L21/485 , H01L23/481 , H01L25/0657 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06596 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599
摘要： As a defective contact recovery elements, a stacked semiconductor device include a parallel arrangement system in which signal paths are multiplexed, and a defective contact recovery circuit operable to switch a signal path into an auxiliary signal path. The parallel arrangement system is used in a case where the number of signals is small and a very high speed operation is required because of a serial data transfer. The defective contact recovery circuit is used in a case where the number of signals is large because of a parallel data transfer.
摘要翻译：作为有缺陷的接触恢复元件，堆叠半导体器件包括其中信号路径被复用的并行布置系统，以及可操作以将信号路径切换到辅助信号路径的缺陷接触恢复电路。在串行数据传输的情况下，使用并行布置系统，并且需要非常高速的操作。在由于并行数据传送而导致信号数量大的情况下使用有缺陷接触恢复电路。

48. 发明申请

US20070126105A1 Stacked type semiconductor memory device and chip selection circuit 失效
标题翻译：堆叠型半导体存储器件和芯片选择电路
公开(公告)号：US20070126105A1
公开(公告)日：2007-06-07
申请号：US11634144
申请日：2006-12-06
申请人： Junji Yamada , Hiroaki Ikeda , Kayoko Shibata , Yoshihiko Inoue , Hitoshi Miwa , Tatsuya Ijima
发明人： Junji Yamada , Hiroaki Ikeda , Kayoko Shibata , Yoshihiko Inoue , Hitoshi Miwa , Tatsuya Ijima
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/04 , G11C2029/4402 , H01L2224/16145 , H01L2225/06513 , H01L2924/01021 , H01L2924/15311
摘要： A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.
摘要翻译：通过分配彼此不同的多个芯片标识号，具有堆叠多个半导体芯片的结构和可以选择期望的半导体芯片的堆叠型半导体存储器件被分别分配给多个半导体芯片，包括：多个操作电路，其以所述多个半导体芯片的堆叠顺序级联连接，并通过执行预定的操作输出所述多个不同的识别号码; 以及多个比较电路，通过比较它们来检测每个半导体芯片共同连接的每个识别号码和芯片选择地址是否相等。

49. 发明授权

US07209376B2 Stacked semiconductor memory device 有权
标题翻译：堆叠半导体存储器件
公开(公告)号：US07209376B2
公开(公告)日：2007-04-24
申请号：US11151213
申请日：2005-06-14
申请人： Hideaki Saito , Yasuhiko Hagihara , Muneo Fukaishi , Masayuki Mizuno , Hiroaki Ikeda , Kayoko Shibata
发明人： Hideaki Saito , Yasuhiko Hagihara , Muneo Fukaishi , Masayuki Mizuno , Hiroaki Ikeda , Kayoko Shibata
IPC分类号： G11C5/06
CPC分类号： G11C5/04 , G11C5/063 , H01L25/0657 , H01L2224/16145 , H01L2225/06527 , H01L2225/06555 , H01L2924/01019 , H01L2924/10253 , H01L2924/00
摘要： A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.
摘要翻译：具有减少在数据传送期间需要充电和放电并因此降低功耗的互连电容的目的的三维半导体存储器件具有：多个存储单元阵列芯片，其中作为分区的子行组合存储器并且被布置为对应于输入/输出位，堆叠在第一半导体芯片上; 以及用于连接存储单元阵列的芯片间互连，使得子组的相应输入/输出位相同，这些芯片间互连以与输入/输出位数相对应的数量提供并通过存储单元阵列芯片在堆叠的方向。

50. 发明申请

US20070005876A1 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US20070005876A1
公开(公告)日：2007-01-04
申请号：US11440398
申请日：2006-05-25
申请人： Hiroaki Ikeda , Mamoru Sasaki , Atsushi Iwata
发明人： Hiroaki Ikeda , Mamoru Sasaki , Atsushi Iwata
IPC分类号： G06F12/00
CPC分类号： G11C7/1051 , G11C5/02 , G11C7/1039 , G11C7/1078 , G11C7/1087 , G11C2207/107 , H01L23/481 , H01L2224/05573 , H01L2224/13025 , H01L2224/16 , H01L2924/00014 , H01L2924/13091 , H01L2924/00 , H01L2224/05599
摘要： Data transfer speed is increased in a semiconductor storage device in which the core unit and the interface unit are separate chips. The device has a plurality of core chips through in which a memory cell is formed, and an interface chip in which a peripheral circuit is formed for the memory cell. The plurality of core chips through have latch circuit units through for temporarily storing data to be outputted by the memory cell, and latch circuit units through for temporarily storing data to be inputted to the memory cell, respectively, and these latch circuit units through and latch circuit units through are connected in a cascade to the interface chip. Since the plurality of latch circuit units connected in a cascade can thereby perform a pipeline operation, it becomes possible to achieve high-speed data transfer.
摘要翻译：在核心单元和接口单元是分离的芯片的半导体存储设备中，数据传输速度增加。该装置具有通过其中形成有存储单元的多个核芯片，以及形成用于存储单元的外围电路的接口芯片。多个核芯片通过具有用于临时存储由存储单元输出的数据的锁存电路单元，以及用于临时存储要输入到存储单元的数据的锁存电路单元，并且这些锁存电路单元通过和锁存电路单元通过级联连接到接口芯片。由于串联连接的多个锁存电路单元能够进行流水线运行，因此能够实现高速数据传送。

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