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41. 发明授权

US07378863B2 Synchronous semiconductor device, and inspection system and method for the same 失效
标题翻译：同步半导体器件及其检测系统及方法相同
公开(公告)号：US07378863B2
公开(公告)日：2008-05-27
申请号：US11014789
申请日：2004-12-20
申请人： Hiroyuki Sugamoto , Hidetoshi Tanaka , Yasushige Ogawa
发明人： Hiroyuki Sugamoto , Hidetoshi Tanaka , Yasushige Ogawa
IPC分类号： G01R31/28
CPC分类号： G11C8/08 , G01R31/31701 , G11C29/34
摘要： The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
摘要翻译：本发明提供了一种同步半导体装置，其适用于提高对装置的电应力的效率，检查系统及其检查方法，以便有效地执行老化压力试验。具有访问命令输入的命令锁存电路将输出与外部时钟同步的低电平脉冲。脉冲将通过测试模式序列电路的NAND门和公共NAND门，以输出低电平的内部预充电信号，这将使来自控制电路的字线激活信号复位。同时，通过NAND门的内部预充电信号将被内部定时器延迟预定时间段，以通过NAND门输出低电平内部有效信号，该低电平内部有效信号将设置来自控制电路的字线激活信号。

42. 发明授权

US07353469B2 Method and program for designing semiconductor device 有权
标题翻译：设计半导体器件的方法和程序
公开(公告)号：US07353469B2
公开(公告)日：2008-04-01
申请号：US11097204
申请日：2005-04-04
申请人： Yasushige Ogawa
发明人： Yasushige Ogawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78 , Y02E60/76 , Y04S40/22
摘要： It is an object of the present invention to provide a semiconductor device design method and program that can rapidly improve power supply noise characteristics and reduce the noise sufficiently without being restricted in design and noise solution. A step of performing frequency analysis on a power supply distribution network model creates a power supply distribution network model based on electric characteristics obtained in accordance with specifications (maximum allowable drop value of power supply voltage, power supply current value, operating frequency, etc.) of the semiconductor device and performs frequency analysis on this power supply distribution network model. A step of performing frequency analysis based on an operating current waveform analyzes power supply current characteristics based on an operating current waveform obtained in accordance with the specification. A step of calculating power supply noise calculates the power supply noise in accordance with analysis results of the step of performing frequency analysis on the power supply distribution network model and the step of performing frequency analysis based on the operating current waveform. It is thus possible to estimate the power supply noise before designing a circuit of the semiconductor device.
摘要翻译：本发明的一个目的是提供一种半导体器件的设计方法和程序，其可以在不受设计和噪声解决方案的限制的情况下，迅速地提高电源噪声特性并减少噪声。在电源分配网络模型上执行频率分析的步骤基于根据规格获得的电特性（电源电压的最大允许下降值，电源电流值，工作频率等）创建电力分配网络模型，并对该电源分配网络模型进行频率分析。基于工作电流波形执行频率分析的步骤基于根据说明书获得的工作电流波形来分析电源电流特性。计算电源噪声的步骤根据对电源分配网络模型进行频率分析的步骤的分析结果和基于工作电流波形执行频率分析的步骤来计算电源噪声。因此，可以在设计半导体器件的电路之前估计电源噪声。

43. 发明申请

US20070222531A1 Oscillator circuit, semiconductor device and semiconductor memory device provided with the oscillator circuit, and control method of the oscillator circuit 有权
标题翻译：振荡器电路，半导体器件和配有振荡电路的半导体存储器件，以及振荡电路的控制方法
公开(公告)号：US20070222531A1
公开(公告)日：2007-09-27
申请号：US11802637
申请日：2007-05-24
申请人： Yasushige Ogawa , Satoru Kawamoto
发明人： Yasushige Ogawa , Satoru Kawamoto
IPC分类号： H03B5/04
CPC分类号： G06F1/04 , G11C7/22 , G11C7/222 , G11C11/406 , G11C11/4074 , G11C2207/2227 , G11C2211/4067 , H03K3/012 , H03K3/014 , H03K3/0315 , H03K5/1252 , H03K5/19 , H03L3/00
摘要： There is provided an oscillator circuit capable of obtaining stable frequency by avoiding output having unstable frequency that is likely to occur to an operation/stop-control-feasible type oscillator circuit when oscillation begins. In such an oscillator circuit, an oscillation permitting signal (EN) sets an oscillator section in oscillation-operable state, whereby a controller section starts operation. The controller section that has stared its operation change an oscillation- frequency control signal (VR) into a signal value corresponding to predetermined oscillation frequency so as to set oscillation frequency at an oscillator section. Further on, the oscillator section outputs an oscillation signal in response to a detection signal (MON) that is outputted after a detector section compares a signal inputted therein with a predetermined signal value and detects that the inputted signal reaches a predetermined signal value. Thereby, transient state of an oscillation-frequency control signal (VR) can be detected. That is, there can be avoided an output of an unstable oscillation signal due to a transient oscillation-frequency control signal (VR).
摘要翻译：提供了一种振荡器电路，其能够通过在振荡开始时避免可能发生在操作/停止控制可行型振荡器电路的频率不稳定的输出而获得稳定的频率。在这种振荡电路中，振荡允许信号（EN）将振荡器部分置于振荡可操作状态，由此控制器部分开始工作。已经看到其操作的控制器部分将振荡频率控制信号（VR）改变成对应于预定振荡频率的信号值，以便在振荡器部分设置振荡频率。此外，振荡器部分响应于在检测器部分将输入的信号与预定信号值进行比较之后输出的检测信号（MON）输出振荡信号，并检测输入信号达到预定信号值。由此，可以检测振荡频率控制信号（VR）的瞬态。也就是说，可以避免由于瞬态振荡频率控制信号（VR）引起的不稳定振荡信号的输出。

44. 发明申请

US20070170929A1 Control apparatus, semiconductor integrated circuit apparatus, and source voltage supply control system 有权
标题翻译：控制装置，半导体集成电路装置和源电压供给控制系统
公开(公告)号：US20070170929A1
公开(公告)日：2007-07-26
申请号：US11723599
申请日：2007-03-21
申请人： Yasushige Ogawa
发明人： Yasushige Ogawa
IPC分类号： G01R27/02
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： An excluding unit is controlled by a control signal received from a control unit, and based on the control signal a determination is made for each of circuit blocks as to whether either a voltage signal at a position of its corresponding circuit block or a signal indicating a voltage is outputted to a selection unit. From a circuit block which is not in operation, the voltage, but not a voltage signal at a position of the circuit block, is outputted to the selection unit. By this, the circuit block which is not in operation cannot be judged to have voltage drop, and accordingly, a high supply voltage cannot be supplied. Consequently, a malfunction caused by supply voltages to other circuit blocks being too high does not occur.
摘要翻译：排除单元由从控制单元接收到的控制信号控制，并且基于控制信号，确定每个电路块是关于其相应电路块的位置处的电压信号还是指示相应电路块的信号电压被输出到选择单元。从不工作的电路块，电路块的电压而不是电压信号被输出到选择单元。由此，不能判断不工作的电路块具有电压降，因此不能提供高电源电压。因此，不会发生由其他电路块的电源电压引起的故障。

45. 发明申请

US20050270871A1 Semiconductor integrated circuit device, and adjustment method of semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路器件及半导体集成电路器件的调整方法
公开(公告)号：US20050270871A1
公开(公告)日：2005-12-08
申请号：US11198225
申请日：2005-08-08
申请人： Yasushige Ogawa , Yoshiyuki Ishida , Masato Matsumiya
发明人： Yasushige Ogawa , Yoshiyuki Ishida , Masato Matsumiya
IPC分类号： H01L27/04 , G01R31/3167 , H01L21/822 , H03M1/10 , H03M1/66 , G11C7/00
CPC分类号： H03M1/1019 , G01R31/3167 , H03M1/66
摘要： It is intended to provide a semiconductor integrated circuit device and adjustment method of the same semiconductor integrated circuit device, capable of adjusting an analog signal outputted from an incorporated analog signal generating section without outputting it outside as an analog value. An analog signal AOUT is outputted from an analog signal generating section 3 in which an adjustment signal AD is inputted. The analog signal AOUT is inputted to a judgment section 1, in which it is compared and judged with a predetermined value and then a judgment signal JG is outputted. The judgment signal JG acts on a predetermined signal storing section 4 as an internal signal and the adjustment signal AD is fetched into the predetermined signal storing section 4. Further, the judgment signal JG is outputted as digital signal through an external terminal T2 and an external tester device acquires the adjustment signal and stores the acquired adjustment signal in the predetermined signal storing section 4. Consequently, the analog signal can be adjusted as analog value without being outputted outside and an adjustment test can be carried out with a simple tester device and according to a simple test method accurately and rapidly.
摘要翻译：本发明旨在提供一种半导体集成电路器件的半导体集成电路器件和调整方法，该半导体集成电路器件能够调整从内置的模拟信号产生部分输出的模拟信号而不将其输出为模拟值。从输入调整信号AD的模拟信号生成部3输出模拟信号AOUT。模拟信号AOUT被输入到判断部分1，在判定部分1中，以预定值进行比较和判断，然后输出判断信号JG。判断信号JG作为内部信号作用于预定信号存储部分4，并且调节信号AD被取出到预定信号存储部分4.此外，判断信号JG通过外部端子T 2作为数字信号输出，外部测试器装置获取调整信号并将获取的调节信号存储在预定信号存储部分4中。因此，可以将模拟信号调整为模拟值而不输出到外部，并且可以使用简单的测试装置进行调整测试，根据简单的测试方法准确快速。

46. 发明授权

US06700437B1 Semiconductor device including logic circuit and macro circuit which has a function for stopping a direct current 有权
标题翻译：包括逻辑电路和诸如存储电路的宏电路的半导体器件，其具有用于停止直流电的功能
公开(公告)号：US06700437B1
公开(公告)日：2004-03-02
申请号：US09642937
申请日：2000-08-22
申请人： Yasushige Ogawa , Yoshiyuki Ishida
发明人： Yasushige Ogawa , Yoshiyuki Ishida
IPC分类号： G05F110
CPC分类号： G11C29/12005 , G11C7/1006 , G11C7/22 , G11C29/02 , G11C2029/0401 , G11C2029/5006 , G11C2207/2227
摘要： A semiconductor device includes both a logic circuit and a macro circuit. The macro circuit includes a circuit that consumes direct current (DC). In order to conserve power and allow for testing, the consumption of DC by the current consumption circuit can be stopped with a stop signal, which stops the operation of the macro circuit. The macro circuit can be restarted or returned to normal operation mode without risk of error caused by the stopping of the macro circuit.
摘要翻译：半导体器件包括逻辑电路和宏电路。宏电路包括消耗直流（DC）电路。为了节省电力并允许测试，可以通过停止信号停止由电流消耗电路消耗的DC，从而停止宏电路的操作。宏电路可以重启或恢复正常工作模式，而不会由于宏电路停止而引起误差。

47. 发明授权

US06269033B1 Semiconductor memory device having redundancy unit for data line compensation 有权
标题翻译：半导体存储器件具有用于数据线补偿的冗余单元
公开(公告)号：US06269033B1
公开(公告)日：2001-07-31
申请号：US09480619
申请日：2000-01-10
申请人： Yoshiyuki Ishida , Yasushige Ogawa
发明人： Yoshiyuki Ishida , Yasushige Ogawa
IPC分类号： G11C702
CPC分类号： G11C29/848
摘要： A semiconductor memory device, such as a SDRAM, includes input/output data line pairs, data bus line pairs, and a redundancy data bus line pair. The input/output data line pairs are connected to a corresponding one of the data bus line pairs and an adjacent one of the data bus line pairs via redundancy shift switches, with a last one of the input/output data line pairs being connected to a last one fo the data bus line pairs and the redundancy data bus line pair. Sense buffers and write amplifiers are connected between each of the data bus line pairs and the redundancy data line pair. The shift switches are located closer to the input/output data line pairs than the sense buffers and the write amplifiers so that data read from the memory cells is less effected by the on resistance and the parasitic capacitance of the switches. When the switches are located closer to the data bus lines than the sense buffers and the write amplifiers are, the switches effect the data signals of data read from the memory cells.
摘要翻译：诸如SDRAM的半导体存储器件包括输入/输出数据线对，数据总线线对和冗余数据总线对。输入/输出数据线对通过冗余移位开关连接到数据总线线对中的相应一条数据总线线对，其中最后一条输入/输出数据线对连接到最后一个数据总线线对和冗余数据总线对。读数缓冲器和写放大器连接在每个数据总线线对和冗余数据线对之间。移位开关位于比读出缓冲器和写入放大器更靠近输入/输出数据线对的位置，使得从存储器单元读取的数据不受开关的导通电阻和寄生电容的影响。当开关位于比读取缓冲器和写入放大器更靠近数据总线时，开关影响从存储器单元读取的数据的数据信号。

48. 发明授权

US08174282B2 Leak current detection circuit, body bias control circuit, semiconductor device, and semiconductor device testing method 有权
标题翻译：泄漏电流检测电路，体偏置控制电路，半导体器件和半导体器件测试方法
公开(公告)号：US08174282B2
公开(公告)日：2012-05-08
申请号：US12576670
申请日：2009-10-09
申请人： Kiyonaga Fujii , Yasushige Ogawa
发明人： Kiyonaga Fujii , Yasushige Ogawa
IPC分类号： G01R31/02 , G01R31/28
CPC分类号： G01R31/2621 , G01R31/2884 , G01R31/3008 , G01R31/3012
摘要： A leak current detection circuit that improves the accuracy for detecting a leak current in a MOS transistor without enlarging the circuit scale. The leak current detection circuit includes at least one P-channel MOS transistor which is coupled to a high potential power supply and which is normally inactivated and generates a first leak current, at least one N-channel MOS transistor which is coupled between a low potential power and at least the one P-channel MOS transistor and which is normally inactivated and generates a second leak current, and a detector which detects a potential generated at a node between the at least one P-channel MOS transistor and the at least one N-channel MOS transistor in accordance with the first and second leak currents.
摘要翻译：一种泄漏电流检测电路，其提高了在不增加电路规模的情况下检测MOS晶体管中的漏电流的精度。泄漏电流检测电路包括耦合到高电位电源的至少一个P沟道MOS晶体管，其通常是非激活的并且产生第一漏电流，至少一个N沟道MOS晶体管耦合在低电位功率和至少一个P沟道MOS晶体管，并且其通常被非激活并产生第二漏电流;以及检测器，其检测在所述至少一个P沟道MOS晶体管和所述至少一个N之间的节点处产生的电位 - 沟道MOS晶体管，根据第一和第二漏电流。

49. 发明申请

US20100052727A1 SYNCHRONOUS SEMICONDUCTOR DEVICE, AND INSPECTION SYSTEM AND METHOD FOR THE SAME 审中-公开
标题翻译：同步半导体器件及其检测系统及其方法
公开(公告)号：US20100052727A1
公开(公告)日：2010-03-04
申请号：US12614713
申请日：2009-11-09
申请人： Hiroyuki SUGAMOTO , Hidetoshi Tanaka , Yasushige Ogawa
发明人： Hiroyuki SUGAMOTO , Hidetoshi Tanaka , Yasushige Ogawa
IPC分类号： G01R31/28
CPC分类号： G11C8/08 , G01R31/31701 , G11C29/34
摘要： The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carry out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will resent a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
摘要翻译：本发明提供一种同步半导体装置，其适用于提高对装置的电应力的效率，检查系统及其检查方法，以便有效地进行老化应力试验。具有访问命令输入的命令锁存电路将输出与外部时钟同步的低电平脉冲。脉冲将通过测试模式序列电路的NAND门和公共NAND门，以输出低电平的内部预充电信号，这将使来自控制电路的字线激活信号重新发出。同时，通过NAND门的内部预充电信号将被内部定时器延迟预定时间段，以通过NAND门输出低电平内部有效信号，该低电平内部有效信号将设置来自控制电路的字线激活信号。

50. 发明授权

US07663392B2 Synchronous semiconductor device, and inspection system and method for the same 失效
标题翻译：同步半导体器件及其检测系统及方法相同
公开(公告)号：US07663392B2
公开(公告)日：2010-02-16
申请号：US12112782
申请日：2008-04-30
申请人： Hiroyuki Sugamoto , Hidetoshi Tanaka , Yasushige Ogawa
发明人： Hiroyuki Sugamoto , Hidetoshi Tanaka , Yasushige Ogawa
IPC分类号： G01R31/28 , G11C7/00
CPC分类号： G11C8/08 , G01R31/31701 , G11C29/34
摘要： The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
摘要翻译：本发明提供了一种同步半导体装置，其适用于提高对装置的电应力的效率，检查系统及其检查方法，以便有效地执行老化压力试验。具有访问命令输入的命令锁存电路将输出与外部时钟同步的低电平脉冲。脉冲将通过测试模式序列电路的NAND门和公共NAND门，以输出低电平的内部预充电信号，这将使来自控制电路的字线激活信号复位。同时，通过NAND门的内部预充电信号将被内部定时器延迟预定时间段，以通过NAND门输出低电平内部有效信号，该低电平内部有效信号将设置来自控制电路的字线激活信号。

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