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41. 发明授权

US08098191B1 Electronic curtain for vehicle protection 失效
标题翻译：电子窗帘车辆保护
公开(公告)号：US08098191B1
公开(公告)日：2012-01-17
申请号：US12265063
申请日：2008-11-05
申请人： Albert N. Pergande , Lloyd Dan Griffin, Jr. , Steven G. Gray , Hung Q. Le , Steve T. Nicholas
发明人： Albert N. Pergande , Lloyd Dan Griffin, Jr. , Steven G. Gray , Hung Q. Le , Steve T. Nicholas
IPC分类号： G01S13/87 , G01S13/88 , G01S13/00
CPC分类号： G01S13/87 , F41H5/007 , F41H11/02 , G01S13/28 , G01S13/32 , G01S13/582 , G01S13/88
摘要： An apparatus and method for protecting against incoming projectiles comprising transmitting two radar waveforms, the first waveform comprising a pulsed continuous wave waveform, and the second waveform comprising a pulsed linear chirp waveform over a bandwidth, and based on returned radar data, causing deployment of a defense mechanism to intercept a detected incoming projectile.
摘要翻译：一种用于防止入射的射弹的装置和方法，包括传输两个雷达波形，第一波形包括脉冲连续波波形，第二波形包括带宽上的脉冲线性啁啾波形，并且基于返回的雷达数据，拦截侦察到的射弹的防御机制。

42. 发明授权

US06510522B1 Apparatus and method for providing access security to a device coupled upon a two-wire bidirectional bus 有权
标题翻译：用于向耦合在双线双向总线上的设备提供访问安全性的装置和方法
公开(公告)号：US06510522B1
公开(公告)日：2003-01-21
申请号：US09196849
申请日：1998-11-20
申请人： David F. Heinrich , Hung Q. Le , Paul B. Rawlins , Charles J. Stancil
发明人： David F. Heinrich , Hung Q. Le , Paul B. Rawlins , Charles J. Stancil
IPC分类号： H04L900
CPC分类号： G06F21/70 , G06F21/78
摘要： A computer system, bus interface unit, and method are provided for securing certain devices connected to an I2C bus. Those devices include any device which contains sensitive information or passwords. For example, a device controlled by a I2C-connected device bay controller may contain sensitive files, data, and information to which improper access may be denied by securing the device bay controller. Moreover, improper accesses to passwords contained in non-volatile memory connected to the I2C bus must also be prevented. A bus interface unit coupled within the computer contains registers, and logic which compares the incoming I2C target and word addresses with coded bits within fields of those registers. If the target or word address is to a protected address or range of addresses, then an unlock signal must be issued before the security control logic will allow the target or word address to access the I2C bus or addressed device thereon. The unlock signal can be assigned to a particular slot among numerous slots, wherein the slots are arranged in hierarchical order. This allows a system administrator the capability to unlock accesses to protected non-volatile memory, and thereby allowing the system administrator to change passwords within one portion of non-volatile memory, and possibly allowing a lower priority user to access and change a password within another portion of non-volatile memory. The slot which accommodates an unlock signal assigned to the system administrator is altogether separate from a slot assigned to a non-system administrator or user.
摘要翻译：提供了一种计算机系统，总线接口单元和方法，用于固定连接到I2C总线的某些设备。这些设备包括任何包含敏感信息或密码的设备。例如，由I2C连接的设备托架控制器控制的设备可能包含敏感的文件，数据和信息，通过保护设备托架控制器，可能会拒绝访问不正确。此外，还必须防止连接到I2C总线的非易失性存储器中包含的密码访问不正确。耦合在计算机内的总线接口单元包含寄存器和将输入的I2C目标和字地址与这些寄存器的字段内的编码位进行比较的逻辑。如果目标或字地址是受保护的地址或地址范围，则在安全控制逻辑将允许目标或字地址访问I2C总线或寻址设备之前必须发出解锁信号。解锁信号可以分配给多个时隙中的特定时隙，其中时隙按照分级顺序排列。这允许系统管理员解锁对受保护的非易失性存储器的访问的能力，从而允许系统管理员在非易失性存储器的一部分内更改密码，并且可能允许较低优先级的用户访问并改变另一个内部的密码部分非易失性存储器。容纳分配给系统管理员的解锁信号的插槽与分配给非系统管理员或用户的插槽完全分开。

43. 发明授权

US06370649B1 Computer access via a single-use password 失效
标题翻译：计算机通过一次性密码访问
公开(公告)号：US06370649B1
公开(公告)日：2002-04-09
申请号：US09033192
申请日：1998-03-02
申请人： Michael F. Angelo , David F. Heinrich , Hung Q. Le , Richard O. Waldorf
发明人： Michael F. Angelo , David F. Heinrich , Hung Q. Le , Richard O. Waldorf
IPC分类号： H04K100
CPC分类号： G06F21/31 , G06F2221/2131
摘要： A computer system according to the present invention implements a self-modifying “fail-safe” password system that allows a manufacturer or site administrator to securely supply a single-use password to users who lose a power-up password. The fail-safe password system utilizes at least one fail-safe counter, an encryption/decryption algorithm, a public key, and a secure non-volatile memory space. The fail-safe password is derived by generating a hash code using SHA, MD5,or a similar algorithm and encrypting the result. The fail-safe password is then communicated to the user. After the user enters the fail-safe password, the computer system generates an internal hash value and compares it with the hash code of the decrypted fail-safe password. When the decrypted fail-safe password matches the internal hash value, the user is allowed access to the computer system.
摘要翻译：根据本发明的计算机系统实现了自修改“故障安全”密码系统，其允许制造商或站点管理员向失去开机密码的用户安全地提供一次性密码。故障安全密码系统使用至少一个故障安全计数器，加密/解密算法，公钥和安全非易失性存储器空间。故障安全密码是通过使用SHA，MD5或类似算法生成哈希码而得到的，并加密结果。然后将故障安全密码传送给用户。用户输入故障安全密码后，计算机系统会生成内部散列值，并将其与解密的故障安全密码的哈希码进行比较。当解密的故障安全密码与内部散列值匹配时，允许用户访问计算机系统。

44. 发明授权

US09870233B2 Initializing a memory subsystem of a management controller 有权
公开(公告)号：US09870233B2
公开(公告)日：2018-01-16
申请号：US13697972
申请日：2010-05-28
申请人： David F. Heinrich , Theodore F. Emerson , Hung Q. Le
发明人： David F. Heinrich , Theodore F. Emerson , Hung Q. Le
IPC分类号： G06F9/44 , G06F11/14 , G06F11/30
CPC分类号： G06F9/4411 , G06F11/1417 , G06F11/3037 , G06F11/3051
摘要： A method for initializing a memory subsystem (212) of a management controller (200) includes, with an additional memory initialization module (206) of the management controller (200), initializing the memory subsystem (212) of the management controller (200) in response to the memory subsystem (212) not being properly initialized. A management controller (200) includes a memory subsystem (212) including a memory controller (214) and a memory (216); firmware (208) able to initialize the memory subsystem (212); and a memory initialization module (206) to initialize the memory subsystem (212) if the memory subsystem (212) is not properly initialized.

45. 发明授权

US09037837B2 Hardware assist thread for increasing code parallelism 有权
标题翻译：用于增加代码并行性的硬件辅助线程
公开(公告)号：US09037837B2
公开(公告)日：2015-05-19
申请号：US13438087
申请日：2012-04-03
申请人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
发明人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/30101 , G06F9/30149 , G06F9/30189
摘要： Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.
摘要翻译：提供了将工作负载从主线程卸载到辅助线程的机制。机构在数据处理系统的处理器的提取单元中接收主线程的分支到辅助线程指令。分支到辅助线程指令通知处理器的硬件来查找已经产生的空闲线程以用作辅助线程。硬件实现的普遍线程控制逻辑确定一个或多个已经产生的空闲线程是否可用作辅助线程。如果确定一个或多个已经产生的空闲线程可用作辅助线程，则实现的普遍线程控制逻辑的硬件从一个或多个已经产生的空闲线程中选择空闲线程，从而提供辅助线程。此外，实现的普遍线程控制逻辑的硬件将主线程的一部分工作量卸载到辅助线程。

46. 发明授权

US08738995B2 Memory subsystem having a first portion to store data with error correction code information and a second portion to store data without error correction code information 有权
标题翻译：存储器子系统具有用于存储具有纠错码信息的数据的第一部分和用于存储没有纠错码信息的数据的第二部分
公开(公告)号：US08738995B2
公开(公告)日：2014-05-27
申请号：US13384678
申请日：2009-09-10
申请人： Theodore F. Emerson , David F. Heinrich , Hung Q. Le
发明人： Theodore F. Emerson , David F. Heinrich , Hung Q. Le
IPC分类号： G11C29/00
CPC分类号： G06F11/1052
摘要： A system comprising a memory subsystem having at least one memory device, and a memory controller to control access of the memory subsystem, wherein the memory controller is configured to store data with error correction code (ECC) information in a first portion of the memory subsystem, and to store data without ECC information in a second portion of the memory subsystem.
摘要翻译：一种包括具有至少一个存储器装置的存储器子系统和用于控制存储器子系统的访问的存储器控制器的系统，其中所述存储器控制器被配置为在所述存储器子系统的第一部分中存储具有纠错码（ECC）信息的数据并且在存储子系统的第二部分中存储没有ECC信息的数据。

47. 发明授权

US08683175B2 Seamless interface for multi-threaded core accelerators 有权
标题翻译：多线程核心加速器的无缝界面
公开(公告)号：US08683175B2
公开(公告)日：2014-03-25
申请号：US13048214
申请日：2011-03-15
申请人： Kattamuri Ekanadham , Hung Q. Le , Jose E. Moreira , Pratap C. Pattnaik
发明人： Kattamuri Ekanadham , Hung Q. Le , Jose E. Moreira , Pratap C. Pattnaik
IPC分类号： G06F9/30 , G06F12/10
CPC分类号： G06F9/3877 , G06F9/30043 , G06F9/3012 , G06F9/30123 , G06F9/3851 , G06F12/1027
摘要： A method, system and computer program product are disclosed for interfacing between a multi-threaded processing core and an accelerator. In one embodiment, the method comprises copying from the processing core to the hardware accelerator memory address translations for each of multiple threads operating on the processing core, and simultaneously storing on the hardware accelerator one or more of the memory address translations for each of the threads. Whenever any one of the multiple threads operating on the processing core instructs the hardware accelerator to perform a specified operation, the hardware accelerator has stored thereon one or more of the memory address translations for the any one of the threads. This facilitates starting that specified operation without memory translation faults. In an embodiment, the copying includes, each time one of the memory address translations is updated on the processing core, copying the updated one of the memory address translations to the hardware accelerator.
摘要翻译：公开了用于在多线程处理核心和加速器之间进行接口的方法，系统和计算机程序产品。在一个实施例中，该方法包括从处理核心复制到在处理核心上操作的多个线程中的每个线程的硬件加速器存储器地址转换，以及同时在硬件加速器上存储每个线程的一个或多个存储器地址转换。只要在处理核心上操作的多个线程中的任何一个指示硬件加速器执行指定的操作，则硬件加速器在其上存储有针对任何一个线程的一个或多个存储器地址转换。这有助于启动指定的操作，而不会出现内存转换错误。在一个实施例中，复制包括每次在处理核心上更新一个存储器地址转换时，将更新的一个存储器地址转换复制到硬件加速器。

48. 发明申请

US20120254594A1 Hardware Assist Thread for Increasing Code Parallelism 审中-公开
标题翻译：硬件辅助线程增加代码并行性
公开(公告)号：US20120254594A1
公开(公告)日：2012-10-04
申请号：US13438087
申请日：2012-04-03
申请人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
发明人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/30101 , G06F9/30149 , G06F9/30189
摘要： Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.
摘要翻译：提供了将工作负载从主线程卸载到辅助线程的机制。机构在数据处理系统的处理器的提取单元中接收主线程的分支到辅助线程指令。分支到辅助线程指令通知处理器的硬件来查找已经产生的空闲线程以用作辅助线程。硬件实现的普遍线程控制逻辑确定一个或多个已经产生的空闲线程是否可用作辅助线程。如果确定一个或多个已经产生的空闲线程可用作辅助线程，则实现的普遍线程控制逻辑的硬件从一个或多个已经产生的空闲线程中选择空闲线程，从而提供辅助线程。此外，实现的普遍线程控制逻辑的硬件将主线程的一部分工作量卸载到辅助线程。

49. 发明申请

US20110296148A1 Transactional Memory System Supporting Unbroken Suspended Execution 有权
标题翻译：支持不间断暂停执行的事务性内存系统
公开(公告)号：US20110296148A1
公开(公告)日：2011-12-01
申请号：US12788351
申请日：2010-05-27
申请人： Harold W. Cain, III , Bradly G. Frey , Benjamin Herrenschmidt , Hung Q. Le , Cathy May , Maged M. Michael , Jose E. Moreira , Priya A. Nagpurkar , Naresh Nayar , Randal C. Swanberg
发明人： Harold W. Cain, III , Bradly G. Frey , Benjamin Herrenschmidt , Hung Q. Le , Cathy May , Maged M. Michael , Jose E. Moreira , Priya A. Nagpurkar , Naresh Nayar , Randal C. Swanberg
IPC分类号： G06F9/312
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/30189 , G06F9/3834 , G06F9/3842 , G06F9/3859 , G06F9/3863 , G06F9/3865 , G06F9/467
摘要： Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued.
摘要翻译：在具有处理器和事务存储器的数据处理系统中提供用于在数据处理系统中执行事务的机制。这些机制执行包括修改事务存储器的至少一部分的一个或多个指令的事务。响应于由处理器执行的事务挂起指令，事务被暂停。当事务被暂停时，暂停的代码块以非事务方式执行。确定在事务中止时是否发生中断。响应于在事务中止时发生的中断，事务中止操作被延迟，直到事务中止停止为止。

50. 发明授权

US07472258B2 Dynamically shared group completion table between multiple threads 失效
标题翻译：在多个线程之间动态共享组完成表
公开(公告)号：US07472258B2
公开(公告)日：2008-12-30
申请号：US10422654
申请日：2003-04-21
申请人： William E. Burky , Peter J. Klim , Hung Q. Le
发明人： William E. Burky , Peter J. Klim , Hung Q. Le
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/3836 , G06F9/384 , G06F9/3851 , G06F9/3857
摘要： An SMT system has a dynamically shared GCT. Performance for the SMT is improved by configuring the GCT to allow an instruction group from each thread to complete simultaneously. The GCT has a read port for each thread corresponding to the completion table instruction/address array for simultaneous updating on completion. The forward link array also has a read port for each thread to find the next instruction group for each thread upon completion. The backward link array has a backward link write port for each thread in order to update the backward links for each thread simultaneously. The GCT has independent pointer management for each thread. Each of the threads has simultaneous commit of their renamed result registers and simultaneous updating of outstanding load and store tag usage.
摘要翻译： SMT系统具有动态共享的GCT。通过配置GCT来允许每个线程的指令组同时完成，提高了SMT性能。 GCT具有对应于完成表指令/地址数组的每个线程的读端口，用于在完成时同步更新。前向链路阵列还具有每个线程的读取端口，以便在完成时为每个线程找到下一个指令组。反向链路阵列具有用于每个线程的反向链路写入端口，以便同时更新每个线程的反向链路。 GCT对每个线程都有独立的指针管理。每个线程都同时提交其重命名的结果寄存器，并同时更新未完成的负载和存储标签使用。

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