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41. 发明授权

US6011723A Nonvolatile semiconductor memory device including a circuit for providing a boosted potential 有权
公开(公告)号：US6011723A
公开(公告)日：2000-01-04
申请号：US228278
申请日：1999-01-11
申请人： Shigeru Atsumi , Sumio Tanaka
发明人： Shigeru Atsumi , Sumio Tanaka
IPC分类号： H01L21/8247 , G11C16/08 , G11C16/30 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： G11C16/30 , G11C16/08 , H01L27/105
摘要： In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

42. 发明授权

US5892706A Fram, fram card, and card system using the same 失效
标题翻译：框架，框架卡和使用相同的卡片系统
公开(公告)号：US5892706A
公开(公告)日：1999-04-06
申请号：US18693
申请日：1998-02-04
申请人： Mitsuru Shimizu , Sumio Tanaka
发明人： Mitsuru Shimizu , Sumio Tanaka
IPC分类号： G11C5/14 , G11C11/22
CPC分类号： G11C5/14 , G11C11/22
摘要： Circuitry within a ferroelectric memory prevents inversion of the polarization of ferroelectric memory cells caused by a power on reset signal to avoid corruption of data stored therein. A ferroelectric memory includes a memory cell array, a plurality of word lines commonly connected to the gates of the cell transistors in the same row, a plurality of plate lines commonly connected to the plates of the cell capacitors in the same row, a plurality of bit lines commonly connected to one end of the cell transistors in the same row, and a power on reset circuit for generating a power on reset signal of a predetermined level for a predetermined period of time after the power supply is turned on. An erroneous programming prevention circuit within the memory includes a plurality of switching transistors connected between all of the bit lines and plate lines and a plurality of nodes at a predetermined potential. The switching transistors are controlled by the power on reset signal so that they are on for a predetermined period of time.
摘要翻译：铁电存储器内的电路防止由上电复位信号引起的铁电存储器单元极化的反转，以避免存储在其中的数据的损坏。铁电存储器包括存储单元阵列，通常连接到同一行中的单元晶体管的栅极的多个字线，多个板线，共同连接到同一行中的单元电容器的板，多个通常连接到同一行中的单元晶体管的一端的位线，以及在电源接通之后的预定时间段内产生预定电平的上电复位信号的上电复位电路。存储器内的错误编程防止电路包括连接在所有位线和板线之间的多个开关晶体管和预定电位的多个节点。开关晶体管由上电复位信号控制，使得它们在预定时间段内导通。

43. 发明授权

US5812459A Nonvolatile semiconductor memory device having row decoder supplying a negative potential to wordlines during erase mode 失效
标题翻译：具有行解码器的非易失性半导体存储器件在擦除模式期间向字线提供负电位
公开(公告)号：US5812459A
公开(公告)日：1998-09-22
申请号：US805612
申请日：1997-02-26
申请人： Shigeru Atsumi , Sumio Tanaka
发明人： Shigeru Atsumi , Sumio Tanaka
IPC分类号： G11C17/00 , G11C7/00 , G11C8/00 , G11C8/08 , G11C16/06 , G11C16/08 , G11C16/14 , H01L21/8247 , H01L27/10 , H01L27/115
CPC分类号： G11C8/08 , G11C16/08 , G11C16/14
摘要： A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during other modes.
摘要翻译：提供了一种非易失性半导体存储器件，其中在擦除模式期间将负电压施加到存储单元晶体管的栅电极。存储器件包括具有连接到字线的N沟道晶体管的行解码器电路。 N沟道晶体管设置在半导体衬底的P型阱区上。在擦除模式期间，向P型阱区域施加负电压，而在其它模式期间施加接地电位。

44. 发明授权

US5729395A Video tape recorder with liquid crystal display projector having a head drum with fins 失效
标题翻译：具有液晶显示投影仪的磁带录像机具有带有散热片的头鼓
公开(公告)号：US5729395A
公开(公告)日：1998-03-17
申请号：US341889
申请日：1994-11-15
申请人： Sumio Tanaka
发明人： Sumio Tanaka
IPC分类号： G11B15/61 , G11B33/10 , G11B33/14 , G11B15/60
CPC分类号： G11B33/142 , G11B33/10 , G11B15/61
摘要： A Video Tape Recorder (VTR) with a liquid crystal display (LCD) projector free from a radiating blower is disclosed. The VTR with LCD projector includes a plurality of fins positioned on a top surface of a rotary head drum for generating air currents during rotation of a rotary head drum of a VTR part. A polarizing plate of the LCD projector part is cooled by the air currents generated by the fins. The VTR with LCD projector achieves compactness and reduction of cost, in keeping with the recent market trend.
摘要翻译：公开了一种具有不含辐射鼓风机的液晶显示器（LCD）投影仪的录像机（VTR）。具有LCD投影仪的VTR包括位于旋转磁头鼓的顶表面上的多个散热片，用于在VTR部分的旋转磁头鼓旋转期间产生气流。 LCD投影仪部件的偏振片由翅片产生的气流冷却。具有LCD投影机的录像机实现了紧凑性和降低成本，符合最近的市场趋势。

45. 发明授权

US5513146A Nonvolatile semiconductor memory device having a row decoder supplying a negative potential to word lines during erase mode 失效
标题翻译：具有在擦除模式期间向字线提供负电位的行解码器的非易失性半导体存储器件
公开(公告)号：US5513146A
公开(公告)日：1996-04-30
申请号：US358714
申请日：1994-12-19
申请人： Shigeru Atsumi , Sumio Tanaka
发明人： Shigeru Atsumi , Sumio Tanaka
IPC分类号： G11C17/00 , G11C7/00 , G11C8/00 , G11C8/08 , G11C16/06 , G11C16/08 , G11C16/14 , H01L21/8247 , H01L27/10 , H01L27/115
CPC分类号： G11C8/08 , G11C16/08 , G11C16/14
摘要： A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during other modes.
摘要翻译：提供了一种非易失性半导体存储器件，其中在擦除模式期间将负电压施加到存储单元晶体管的栅电极。存储器件包括具有连接到字线的N沟道晶体管的行解码器电路。 N沟道晶体管设置在半导体衬底的P型阱区上。在擦除模式期间，向P型阱区域施加负电压，而在其它模式期间施加接地电位。

46. 发明授权

US5461437A Video tape recorder equipped with liquid crystal display projector 失效
标题翻译：录像机配有液晶显示投影机
公开(公告)号：US5461437A
公开(公告)日：1995-10-24
申请号：US321088
申请日：1994-10-11
申请人： Sumio Tanaka , Yeong J. Joo
发明人： Sumio Tanaka , Yeong J. Joo
IPC分类号： G02F1/13 , G11B20/00 , G11B31/00 , H04N5/74 , H04N5/782 , H04N9/83 , G03B21/10
CPC分类号： H04N5/782 , H04N5/7441 , H04N9/83
摘要： A VTR equipped with an LCD projector integral therewith, capable of eliminating the complexity of wirings and preventing degradation of video signals. The VTR includes a front screen, a rear screen disposed on a front panel of a VCR body and constructed to be openable and closable for the LCD projector projecting the image, a closing detecting unit for detecting an openable or closable state of the rear screen, an image inverting unit for laterally inverting a direction of the image to be projected onto the rear screen, the rear screen being opened when a viewer observes the image projected on the front screen, while being closed when the viewer observes the image projected on the rear screen, the detecting unit informing the image inverting means of the closed state of the rear screen, and the image inverting unit laterally inverting the image to be projected onto the rear screen upon receiving the information.
摘要翻译：配备有与其一体的LCD投影仪的VTR，能够消除布线的复杂性并防止视频信号的劣化。 VTR包括前屏幕，后屏幕，其设置在VCR主体的前面板上，并被构造为可投影图像的LCD投影仪可开启和关闭;闭合检测单元，用于检测后屏幕的可打开或关闭状态，图像反转单元，用于横向反转要投射到后屏幕上的图像的方向，当观察者观察投影在前屏幕上的图像时，后屏幕被打开，同时当观看者观察投影在后面的图像时的图像屏幕，检测单元通知图像反转装置处于后屏幕的关闭状态，并且图像反相单元在接收到信息时横向翻转要投影到图像上的图像。

47. 发明授权

US4974206A Nonvolatile semiconductor memory device having reference potential generating circuit 失效
标题翻译：具有基准电位发生电路的非易失性半导体存储器件
公开(公告)号：US4974206A
公开(公告)日：1990-11-27
申请号：US444986
申请日：1989-12-04
申请人： Yumiko Iyama , Junichi Miyamoto , Nobuaki Ohtsuka , Sumio Tanaka
发明人： Yumiko Iyama , Junichi Miyamoto , Nobuaki Ohtsuka , Sumio Tanaka
IPC分类号： G11C17/00 , G11C16/06 , G11C16/28
CPC分类号： G11C16/28
摘要： A semiconductor memory device includes a memory cell transistor, a voltage switching circuit supplied with a first voltage for data readout and a second voltage for data write and selectively generating one of the first and second voltages in response to a write control signal, a first driving circuit supplied with an output from the voltage switching circuit and driving the gate of the memory cell transistor in response to a memory cell selection signal, a sense circuit for sensing data of the memory cell transistor by comparing a sense potential corresponding to data from the memory cell transistor with a reference potential, a reference cell transistor for generating the reference potential, and a second driving circuit supplied with the output from the voltage switching circuit and driving the gate of the reference cell transistor in response to the write control signal.

48. 发明授权

US4943962A Nonvolatile semiconductor memory having page mode programming function 失效
标题翻译：具有页模式编程功能的非易失性半导体存储器
公开(公告)号：US4943962A
公开(公告)日：1990-07-24
申请号：US263752
申请日：1988-10-28
申请人： Keniti Imamiya , Sumio Tanaka , Junichi Miyamoto , Shigeru Atsumi , Nobuaki Ohtsuka , Shinji Saito
发明人： Keniti Imamiya , Sumio Tanaka , Junichi Miyamoto , Shigeru Atsumi , Nobuaki Ohtsuka , Shinji Saito
IPC分类号： G11C17/00 , G11C16/02 , G11C16/10
CPC分类号： G11C16/10 , G11C2216/14
摘要： A nonvolatile semiconductor memory of this invention is constituted to latch input data into data latch circuits and at the same time control the programming operation of the bit line load transistors when the chip enable signal is made active and a page programming power source voltage is set at the programming voltage, while the output enable signal is kept inactive. Further, when the output enable signal is made active or the programming power source voltage is set at a voltage different from the programming voltage, the data latch circuits are reset. The data latch circuits can be selectively specified by a preset combination of bits.
摘要翻译：本发明的非易失性半导体存储器被构造成将输入数据锁存到数据锁存电路中，同时在芯片使能信号有效时控制位线负载晶体管的编程操作，并将页面编程电源电压设置为编程电压，而输出使能信号保持不活动。此外，当使输出使能信号有效或者将编程电源电压设置为与编程电压不同的电压时，复位数据锁存电路。数据锁存电路可以通过预设的位组合来选择性地指定。

49. 发明授权

US4926070A Voltage level converting circuit 失效
标题翻译：电压电平转换电路
公开(公告)号：US4926070A
公开(公告)日：1990-05-15
申请号：US291933
申请日：1988-12-30
申请人： Sumio Tanaka , Shigeru Atsumi
发明人： Sumio Tanaka , Shigeru Atsumi
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , G11C16/12 , H03K5/02 , H03K19/003 , H03K19/017 , H03K19/0185
CPC分类号： G11C16/12 , H03K19/00361 , H03K19/01721 , H03K19/018521
摘要： A voltage level converting circuit for outputting an output signal of a write voltage level responsive to a read voltage level input signal comprises an inverter circuit biased with a power supply of the first voltage level. The input signal is supplied through a transfer gate circuit. A MOS transistor is provided between the input of the inverter circuit and a power supply of the write voltage level to pull-up the voltage level of the input to the inverter circuit responsive to the output of the inverter circuit. Another MOS transistor is provided between the output of the inverter circuit and ground to pull-down the output voltage level responsive to the input signal.
摘要翻译：用于响应于读取电压电平输入信号输出写入电压电平的输出信号的电压电平转换电路包括用第一电压电平的电源偏置的反相器电路。输入信号通过传输门电路提供。在逆变器电路的输入端和写入电压电平的电源之间设置MOS晶体管，以响应于反相器电路的输出而将输入的电压电平上拉到逆变器电路。另一个MOS晶体管设置在反相器电路的输出端和接地端之间，以响应于输入信号下拉输出电压电平。

50. 发明授权

US4912534A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US4912534A
公开(公告)日：1990-03-27
申请号：US394278
申请日：1989-08-14
申请人： Sumio Tanaka , Shigeru Atsumi , Kenji Shibata , Koichi Kanzaki
发明人： Sumio Tanaka , Shigeru Atsumi , Kenji Shibata , Koichi Kanzaki
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/10 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , G11C16/0441
摘要： A second impurity diffusion layer is formed in a semiconductor substrate at a fixed distance from a first diffusion layer in the substrate. The diffusion layer is supplied with a program potential. An electrode is placed on the channel region between the first and second diffusion layers. Non-selected memory cells are prevented from becoming half-selected by electrically separating the first diffusion layer from the program potential according to signals from the electrode, resulting in substantial improvements in the reliability of the semiconductor device.
摘要翻译：第二杂质扩散层形成在与衬底中的第一扩散层固定距离的半导体衬底中。向扩散层提供程序电位。电极放置在第一和第二扩散层之间的沟道区上。通过根据来自电极的信号将第一扩散层与编程电位进行电分离，防止了未选择的存储单元的半选择，从而显着提高了半导体器件的可靠性。

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