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41. 发明授权

US6124061A Lithium ion secondary battery 失效
标题翻译：锂离子二次电池
公开(公告)号：US6124061A
公开(公告)日：2000-09-26
申请号：US984185
申请日：1997-12-03
申请人： Kouji Hamano , Yasuhiro Yoshida , Hisashi Shiota , Shou Shiraga , Shigeru Aihara , Michio Murai , Takayuki Inuzuka
发明人： Kouji Hamano , Yasuhiro Yoshida , Hisashi Shiota , Shou Shiraga , Shigeru Aihara , Michio Murai , Takayuki Inuzuka
IPC分类号： H01M10/05 , H01M2/16 , H01M4/62 , H01M6/18 , H01M6/40 , H01M10/052 , H01M10/0525 , H01M10/0566 , H01M10/058 , H01M10/0585 , H01M10/0587 , H01M10/36 , H01M10/40
CPC分类号： H01M10/0525 , H01M10/058 , H01M10/0585 , H01M10/0587 , H01M2/1673 , H01M2/1686 , H01M4/622 , H01M2/168 , H01M6/181 , H01M6/40 , Y10T29/49115
摘要： To obtain a lithium ion secondary battery having excellent charge and discharge characteristics in which electric connection between electrodes can be maintained without requiring a strong armor metal case, so that it can be made into thin forms having large energy density. A positive electrode 3 prepared by bonding a positive electrode active material layer 7 to a positive electrode collector 6, a negative electrode 5 prepared by bonding a negative electrode active material layer 9 to a negative electrode collector 10 and a separator 4 which is arranged between these two electrodes and keeps a lithium ion-containing electrolytic solution are closely adhered by bonding the positive electrode active material layer 7 and the negative electrode active material layer 9 to the separator 4 by a porous adhesive resin layer 11, and an electrolytic solution is kept in through holes 12 formed in the adhesive resin layer 11, which communicate the positive electrode active material layer 7 and the negative electrode active material layer 9 with the separator 4.
摘要翻译：为了获得具有优异的充电和放电特性的锂离子二次电池，其中可以保持电极之间的电连接，而不需要强韧的金属外壳，使得其可以制成具有大能量密度的薄形式。通过将正极活性物质层7与正极集电体6接合而制作的正极3，将负极活性物质层9与负极集电体10接合而制作的负极5和配置在这些通过多孔粘合树脂层11将正极活性物质层7和负极活性物质层9接合到隔膜4，使两个电极和保持含锂离子的电解液紧密粘合，将电解液保持在形成在粘合树脂层11中的通孔12，其将正极活性物质层7和负极活性物质层9与隔膜4连通。

42. 发明授权

US6024773A Method of fabricating a lithium ion secondary battery 失效
标题翻译：制造锂离子二次电池的方法
公开(公告)号：US6024773A
公开(公告)日：2000-02-15
申请号：US996319
申请日：1997-12-22
申请人： Takayuki Inuzuka , Yasuhiro Yoshida , Michio Murai , Kouji Hamano , Hisashi Shiota , Shou Shiraga , Shigeru Aihara
发明人： Takayuki Inuzuka , Yasuhiro Yoshida , Michio Murai , Kouji Hamano , Hisashi Shiota , Shou Shiraga , Shigeru Aihara
IPC分类号： H01M4/62 , H01M2/16 , H01M6/40 , H01M10/04 , H01M10/05 , H01M10/052 , H01M10/0566 , H01M10/058 , H01M10/40 , H01M10/38
CPC分类号： H01M10/04 , H01M10/0525 , H01M10/0585 , H01M4/1391 , H01M4/1393 , H01M6/40 , Y02P70/54 , Y10T29/49114 , Y10T29/49115
摘要： To provide a process for producing a lithium ion secondary battery which can have any arbitrary shape, such as thin shape, and yet exhibits high performance. In a method of fabricating a battery comprising a positive electrode 1, a negative electrode 4, and a separator 7, a binder resin solution mainly comprising polyvinylidene fluoride is applied to the separator 7, and the positive electrode 1 and the negative electrode 4 are laid thereon, followed by drying to form a battery laminate, which is then impregnated with an electrolytic solution.
摘要翻译：本发明提供一种锂离子二次电池的制造方法，该锂离子二次电池可以具有任意形状，例如薄形状，但表现出高性能。在制造包括正极1，负极4和隔板7的电池的方法中，将主要包含聚偏二氟乙烯的粘合剂树脂溶液施加到隔板7，并且正极1和负极4被铺设然后干燥以形成电池层压体，然后用电解液浸渍。

43. 发明申请

US20070194433A1 Electronic circuit, a semiconductor device and a mounting substrate 有权
标题翻译：电子电路，半导体器件和安装基板
公开(公告)号：US20070194433A1
公开(公告)日：2007-08-23
申请号：US10592948
申请日：2004-03-19
申请人： Motoo Suwa , Yoshinori Miyaki , Toru Hayashi , Ryoichi Sano , Shigezumi Matsui , Takanobu Naruse , Takashi Sato , Hisashi Shiota
发明人： Motoo Suwa , Yoshinori Miyaki , Toru Hayashi , Ryoichi Sano , Shigezumi Matsui , Takanobu Naruse , Takashi Sato , Hisashi Shiota
IPC分类号： H01L23/12
CPC分类号： H01L23/552 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49171 , H01L2924/00014 , H01L2924/01019 , H01L2924/01055 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/12041 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/0216 , H05K1/023 , H05K1/0246 , H05K1/0248 , H05K1/0298 , H05K1/112 , H05K1/181 , H05K2201/09227 , H05K2201/09236 , H05K2201/09263 , H05K2201/093 , H05K2201/10022 , H05K2201/10159 , H05K2201/10522 , H05K2201/10689 , H05K2201/10734 , Y02P70/611 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electronic circuit includes a first semiconductor device (4) and a second semiconductor device (3) on a mounting substrate. The mounting substrate includes a plurality of mounting substrate lines (201 to 204) which are connected in common with external terminals of a plurality of bits of the first semiconductor device and external terminals of a plurality of bits of the second semiconductor device for every bit. The mounting substrate lines have lengths thereof from the external terminals of the first semiconductor device to the external terminals of the second semiconductor device made unequal for respective bits. Assembling lines (361 to 364) which reach connecting electrodes of a semiconductor chip from the external terminals of the second semiconductor device have made lengths thereof unequal for respective bits. Here, the unequal lengths of the mounting substrate lines have a relationship which offsets the unequal lengths of the assembling lines. According to such a constitution, it is unnecessary to set lengths between the external terminals of the second semiconductor device and the connecting electrodes of the semiconductor chip equal.
摘要翻译：电子电路包括在安装基板上的第一半导体器件（4）和第二半导体器件（3）。安装基板包括与第一半导体器件的多个位的外部端子和第二半导体器件的多个位的外部端子共同连接的多个安装基板线（201〜204）。安装基板线具有从第一半导体器件的外部端子到对于各个位不相等的第二半导体器件的外部端子的长度。从第二半导体器件的外部端子到达半导体芯片的连接电极的组装线（361至364）使其长度对于各个位不相等。这里，安装基板线的不等长度具有抵消装配线的不等长度的关系。根据这种结构，不需要在第二半导体器件的外部端子和半导体芯片的连接电极之间设置长度相等。

44. 发明授权

US07412616B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07412616B2
公开(公告)日：2008-08-12
申请号：US10895394
申请日：2004-07-21
申请人： Shigezumi Matsui , Takashi Sato , Kazuyuki Sakata , Tsuyoshi Yaguchi , Kenzo Kuwabara , Atsushi Nakamura , Motoo Suwa , Ryoichi Sano , Hisashi Shiota
发明人： Shigezumi Matsui , Takashi Sato , Kazuyuki Sakata , Tsuyoshi Yaguchi , Kenzo Kuwabara , Atsushi Nakamura , Motoo Suwa , Ryoichi Sano , Hisashi Shiota
IPC分类号： H04L7/00
CPC分类号： G06F13/4243 , G06F13/1689
摘要： A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.
摘要翻译：存储器接口电路可连接到DDR-SDRAM，其与数据选通信号一起与数据选通信号一起输出读取数据。时钟发生器产生提供给DDR-SDRAM的内部时钟信号和存储器时钟信号。存储器接口电路通过使用相对于DDR-SDRAM在读周期中输入的数据选通信号，相对于相应的内部时钟信号确定数据选通信号的到达延迟，基于信号对所读取的数据进行采样通过移位到达数据选通信号的相位来获得，并且基于到达延迟的确定结果将采样的读取数据与相应的内部时钟信号同步。

45. 发明授权

US07945801B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07945801B2
公开(公告)日：2011-05-17
申请号：US12169853
申请日：2008-07-09
申请人： Shigezumi Matsui , Takashi Sato , Kazuyuki Sakata , Tsuyoshi Yaguchi , Kenzo Kuwabara , Atsushi Nakamura , Motoo Suwa , Ryoichi Sano , Hisashi Shiota
发明人： Shigezumi Matsui , Takashi Sato , Kazuyuki Sakata , Tsuyoshi Yaguchi , Kenzo Kuwabara , Atsushi Nakamura , Motoo Suwa , Ryoichi Sano , Hisashi Shiota
IPC分类号： H04L7/00
CPC分类号： G06F13/4243 , G06F13/1689
摘要： A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.
摘要翻译：存储器接口电路可连接到DDR-SDRAM，其与数据选通信号一起与数据选通信号一起输出读取数据。时钟发生器产生提供给DDR-SDRAM的内部时钟信号和存储器时钟信号。存储器接口电路通过使用相对于DDR-SDRAM在读周期中输入的数据选通信号，相对于相应的内部时钟信号确定数据选通信号的到达延迟，基于信号对所读取的数据进行采样通过移位到达数据选通信号的相位来获得，并且基于到达延迟的确定结果将采样的读取数据与相应的内部时钟信号同步。

46. 发明授权

US07528473B2 Electronic circuit, a semiconductor device and a mounting substrate 有权
标题翻译：电子电路，半导体器件和安装基板
公开(公告)号：US07528473B2
公开(公告)日：2009-05-05
申请号：US10592948
申请日：2004-03-19
申请人： Motoo Suwa , Yoshinori Miyaki , Toru Hayashi , Ryoichi Sano , Shigezumi Matsui , Takanobu Naruse , Takashi Sato , Hisashi Shiota
发明人： Motoo Suwa , Yoshinori Miyaki , Toru Hayashi , Ryoichi Sano , Shigezumi Matsui , Takanobu Naruse , Takashi Sato , Hisashi Shiota
IPC分类号： H01L23/52
CPC分类号： H01L23/552 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49171 , H01L2924/00014 , H01L2924/01019 , H01L2924/01055 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/12041 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/0216 , H05K1/023 , H05K1/0246 , H05K1/0248 , H05K1/0298 , H05K1/112 , H05K1/181 , H05K2201/09227 , H05K2201/09236 , H05K2201/09263 , H05K2201/093 , H05K2201/10022 , H05K2201/10159 , H05K2201/10522 , H05K2201/10689 , H05K2201/10734 , Y02P70/611 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electronic circuit includes a first semiconductor device and a second semiconductor device on a mounting substrate. The mounting substrate lines have lengths which are made unequal for respective bits. Assembling lines which reach connecting electrodes of a semiconductor chip from the external terminals of the second semiconductor device have made lengths thereof unequal for respective bits. The unequal lengths of the mounting substrate lines have a relationship which offsets the unequal lengths of the assembling lines.
摘要翻译：电子电路包括第一半导体器件和安装基板上的第二半导体器件。安装衬底线的长度对于各个位而言是不相等的。从第二半导体器件的外部端子到达半导体芯片的连接电极的组装线使其长度对于各个位不相等。安装基板线的不等长度具有抵消组装线的不等长度的关系。

47. 发明申请

US20050047192A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20050047192A1
公开(公告)日：2005-03-03
申请号：US10895394
申请日：2004-07-21
申请人： Shigezumi Matsui , Takashi Sato , Kazuyuki Sakata , Tsuyoshi Yaguchi , Kenzo Kuwabara , Atsushi Nakamura , Motoo Suwa , Ryoichi Sano , Hisashi Shiota
发明人： Shigezumi Matsui , Takashi Sato , Kazuyuki Sakata , Tsuyoshi Yaguchi , Kenzo Kuwabara , Atsushi Nakamura , Motoo Suwa , Ryoichi Sano , Hisashi Shiota
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G06F15/78 , G11C11/22 , G11C11/401 , G11C11/407
CPC分类号： G06F13/4243 , G06F13/1689
摘要： A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.
摘要翻译：存储器接口电路可连接到DDR-SDRAM，其与数据选通信号一起与数据选通信号一起输出读取数据。时钟发生器产生提供给DDR-SDRAM的内部时钟信号和存储器时钟信号。存储器接口电路通过使用相对于DDR-SDRAM在读周期中输入的数据选通信号，相对于相应的内部时钟信号确定数据选通信号的到达延迟，基于信号对所读取的数据进行采样通过移位到达数据选通信号的相位来获得，并且基于到达延迟的确定结果将采样的读取数据与相应的内部时钟信号同步。

48. 发明申请

US20080276112A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20080276112A1
公开(公告)日：2008-11-06
申请号：US12169853
申请日：2008-07-09
申请人： SHIGEZUMI MATSUI , Takashi Sato , Kazuyuki Sakata , Tsuyoshi Yaguchi , Kenzo Kuwabara , Atsushi Nakamura , Motoo Suwa , Ryoichi Sano , Hisashi Shiota
发明人： SHIGEZUMI MATSUI , Takashi Sato , Kazuyuki Sakata , Tsuyoshi Yaguchi , Kenzo Kuwabara , Atsushi Nakamura , Motoo Suwa , Ryoichi Sano , Hisashi Shiota
IPC分类号： H04L7/00
CPC分类号： G06F13/4243 , G06F13/1689
摘要： A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.
摘要翻译：存储器接口电路可连接到DDR-SDRAM，其与数据选通信号一起与数据选通信号一起输出读取数据。时钟发生器产生提供给DDR-SDRAM的内部时钟信号和存储器时钟信号。存储器接口电路通过使用相对于DDR-SDRAM在读周期中输入的数据选通信号，相对于相应的内部时钟信号确定数据选通信号的到达延迟，基于信号对所读取的数据进行采样通过移位到达数据选通信号的相位来获得，并且基于到达延迟的确定结果将采样的读取数据与相应的内部时钟信号同步。

49. 发明授权

US5672951A Determination and control of battery state 失效
标题翻译：电池状态的测定与控制
公开(公告)号：US5672951A
公开(公告)日：1997-09-30
申请号：US529396
申请日：1995-09-18
申请人： Hisashi Shiota
发明人： Hisashi Shiota
IPC分类号： G01R31/36 , H01M10/44 , H01M10/48 , H02J7/00 , H02J7/10 , H01M10/46
CPC分类号： G01R31/361 , G01R31/3662 , H02J7/0078 , H02J7/008
摘要： A technique for measuring battery characteristics comprises measuring a battery terminal voltage, a charge/discharge current and a charge/discharge time. The technique entails arithmetically determining an integrated power, an integrated charge quantity and an integrating time interval over a period extending from a start of a charge/discharge process to an end thereof, determining a mean terminal voltage by dividing the integrated power by the integrated charge quantity, determining a mean charge current by dividing the integrated charge quantity by the integrating time interval, determining a polarization resistance of the battery on the basis of the mean terminal voltage and the mean current by using a battery polarization resistance model, and finally determining an open-circuit voltage of the battery on the basis of the polarization resistance. The information culled from the above technique may be used to control a charge/discharge process and to predict the remaining life of the battery.
摘要翻译：用于测量电池特性的技术包括测量电池端子电压，充电/放电电流和充电/放电时间。该技术需要在从充电/放电过程开始到其结束的一段时间内算术确定集成电力，积分电荷量和积分时间间隔，通过将积分功率除以积分电荷来确定平均端电压数量，通过将积分电荷量除以积分时间间隔来确定平均充电电流，通过使用电池极化电阻模型，基于平均端电压和平均电流确定电池的极化电阻，最后确定基于极化电阻的电池的开路电压。从上述技术中剔除的信息可用于控制充电/放电过程并预测电池的剩余寿命。

50. 发明授权

US4910101A Stacked type fuel cell 失效
标题翻译：堆叠型燃料电池
公开(公告)号：US4910101A
公开(公告)日：1990-03-20
申请号：US277962
申请日：1988-11-30
申请人： Kenro Mitsuda , Toshiaki Murahashi , Hisashi Shiota
发明人： Kenro Mitsuda , Toshiaki Murahashi , Hisashi Shiota
IPC分类号： H01M8/02 , H01M8/04 , H01M8/24
CPC分类号： H01M8/2465 , H01M8/0289 , H01M8/04119 , H01M8/04283
摘要： A fuel cell having a receiver extending from a side surface of a stacked-cell body of a fuel cell and adapted to receive surplus electrolyte falling along the side surface, and a barrier disposed on the receiver and adapted to catch the electrolyte discharged from a reserve plate while partially restricting an opening which serves as the outlet of a reaction gas flow path. The electrolyte discharged from one single cell can positively be recovered and returned to the same single cell without causing any substantial pressure loss.
摘要翻译：一种燃料电池，具有从燃料电池的层叠电池主体的侧表面延伸并适于容纳沿着侧表面落下的多余电解质的接收器，以及设置在接收器上并适于捕获从储备器排出的电解液的屏障的燃料电池同时部分地限制用作反应气体流路的出口的开口。从单个电池排出的电解液可以正确地回收并返回到相同的单电池，而不会导致任何显着的压力损失。

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