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41. 发明授权

US06757214B2 Synchronous type semiconductor memory device 失效
标题翻译：同步型半导体存储器件
公开(公告)号：US06757214B2
公开(公告)日：2004-06-29
申请号：US10443439
申请日：2003-05-22
申请人： Kazuaki Kawaguchi , Shigeo Ohshima , Nobuo Watanabe , Yoshinori Ogawa
发明人： Kazuaki Kawaguchi , Shigeo Ohshima , Nobuo Watanabe , Yoshinori Ogawa
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/1045 , G11C7/1072
摘要： A synchronous type semiconductor device which inputs/outputs data with respect to a host includes a memory circuit, command decoder and CAS latency setting circuit. The command decoder decodes a command control signal input from the host in synchronism with a clock input from the host and outputs the decoded command to the memory circuit. The command includes a read command and mode register set command. The CAS latency setting circuit sets CAS latency in a read cycle based on a predetermined command output from the command decoder and a function control signal input from the host. The predetermined command is a command other than the mode register set command.
摘要翻译：相对于主机输入/输出数据的同步型半导体器件包括存储器电路，命令解码器和CAS延迟设置电路。命令解码器与从主机输入的时钟同步地解码从主机输入的命令控制信号，并将解码的命令输出到存储器电路。该命令包括读命令和模式寄存器设置命令。 CAS延迟设置电路基于从命令解码器输出的预定命令和从主机输入的功能控制信号在读周期中设置CAS等待时间。预定命令是除模式寄存器设置命令之外的命令。

42. 发明授权

US06731559B2 Synchronous semiconductor memory device 有权
标题翻译：同步半导体存储器件
公开(公告)号：US06731559B2
公开(公告)日：2004-05-04
申请号：US10244962
申请日：2002-09-17
申请人： Kazuaki Kawaguchi , Shigeo Ohshima
发明人： Kazuaki Kawaguchi , Shigeo Ohshima
IPC分类号： G11C700
CPC分类号： G11C7/04 , G11C7/1066 , G11C7/1072
摘要： A synchronous semiconductor memory device has a memory section which includes a memory cell array having a plurality of memory cells and which is capable of a read operation of reading information from the memory cells according to a read command and a write operation of writing information into the memory cells according to a write command. The synchronous semiconductor memory device further has a command sensing circuit which senses whether a first command inputted in synchronization with an external clock signal is the read command or the write command. The synchronous semiconductor memory device further has a bank timer circuit which, when the command sensing circuit has sensed either the read command or the write command, sets the end time of the restore operation of a row address strobe (RAS) and the start time of the precharge operation of the RAS according to the external clock signal.
摘要翻译：同步半导体存储器件具有存储器部分，其包括具有多个存储器单元的存储器单元阵列，并且能够根据读取命令和将信息写入到存储器单元的读取操作从存储器单元读取信息的读取操作内存单元根据写命令。同步半导体存储器件还具有命令检测电路，其检测与外部时钟信号同步输入的第一命令是读命令还是写指令。同步半导体存储器件还具有一个存储体定时器电路，当命令感测电路感测到读取命令或写入命令时，设置行地址选通（RAS）的恢复操作的结束时间和开始时间 RAS的预充电操作根据外部时钟信号。

43. 发明授权

US06463007B2 Synchronous semiconductor memory device 失效
标题翻译：同步半导体存储器件
公开(公告)号：US06463007B2
公开(公告)日：2002-10-08
申请号：US09934691
申请日：2001-08-23
申请人： Hiroyuki Ohtake , Shigeo Ohshima
发明人： Hiroyuki Ohtake , Shigeo Ohshima
IPC分类号： G11C800
CPC分类号： G11C7/1072 , G11C11/4076 , G11C11/4087
摘要： A synchronous semiconductor memory device such as SDRAM easy in timing adjustment of column selection and capable of reducing cycle time and access time to be minimum value without reducing access margin is provided. The synchronous semiconductor memory device includes a memory cell array constituted in a matrix form, a command decoder and an address buffer operative in synchronism with the leading end of clock signal, a row decoder for decoding row address to select word line of the memory cell, a column control signal generating circuit for generating a column control signal, and a column decoder for taking thereinto column address taken in by the address buffer by a column address taking-in signal generated from the command decoder in synchronism with the leading end of the clock signal to allow a column select signal line to be active.
摘要翻译：提供了诸如SDRAM之类的同步半导体存储器件，用于列选择的定时调整，并且能够将循环时间和存取时间缩短为最小值而不减少访问余量。同步半导体存储器件包括以矩阵形式构成的存储单元阵列，命令解码器和与时钟信号的前端同步的地址缓冲器，用于解码行地址以选择存储单元的字线的行解码器，用于产生列控制信号的列控制信号发生电路和列解码器，用于通过与命令解码器产生的列地址取入信号同步于时钟的前端，将列地址缓冲器取入的列地址信号以允许列选择信号线被激活。

44. 发明授权

US06292430B1 Synchronous semiconductor memory device 失效
标题翻译：同步半导体存储器件
公开(公告)号：US06292430B1
公开(公告)日：2001-09-18
申请号：US09526212
申请日：2000-03-15
申请人： Hiroyuki Ohtake , Shigeo Ohshima
发明人： Hiroyuki Ohtake , Shigeo Ohshima
IPC分类号： G11C800
CPC分类号： G11C7/1072 , G11C11/4076 , G11C11/4087
摘要： A synchronous semiconductor memory device such as SDRAM easy in timing adjustment of column selection and capable of reducing cycle time and access time to be minimum value without reducing access margin is provided. The synchronous semiconductor memory device includes a memory cell array constituted in a matrix form, a command decoder and an address buffer operative in synchronism with the leading end of clock signal, a row decoder for decoding row address to select word line of the memory cell, a column control signal generating circuit for generating a column control signal, and a column decoder for taking thereinto column address taken in by the address buffer by a column address taking-in signal generated from the command decoder in synchronism with the leading end of the clock signal to allow a column select signal line to be active.
摘要翻译：提供了诸如SDRAM之类的同步半导体存储器件，用于列选择的定时调整，并且能够将循环时间和存取时间缩短为最小值而不减少访问余量。同步半导体存储器件包括以矩阵形式构成的存储单元阵列，命令解码器和与时钟信号的前端同步的地址缓冲器，用于解码行地址以选择存储单元的字线的行解码器，用于产生列控制信号的列控制信号发生电路和列解码器，用于通过与命令解码器产生的列地址取入信号同步于时钟的前端，将列地址缓冲器取入的列地址信号以允许列选择信号线被激活。

45. 发明授权

US06292412B1 Clock control circuit 有权
标题翻译：时钟控制电路
公开(公告)号：US06292412B1
公开(公告)日：2001-09-18
申请号：US09609145
申请日：2000-06-30
申请人： Koji Kato , Masahiro Kamoshida , Shigeo Ohshima , Hiroyuki Ohtake
发明人： Koji Kato , Masahiro Kamoshida , Shigeo Ohshima , Hiroyuki Ohtake
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/22
摘要： A clock synchronous circuit comprising a clock receiver, a delay monitor, a forward pulse delay circuit, a backward pulse delay circuit, a driver, a state-holding section, a control signal generating circuit, a first AND circuit, and a second AND circuit. The delay monitor delays the output of the clock receiver. The forward pulse delay circuit delays the output of the delay monitor. The backward pulse delay circuit delays the output of the clock receiver. The driver receives the output of the backward pulse delay circuit and outputs an internal clock signal. The state-holding section controls the backward pulse delay circuit. The control pulse generating circuit initializes the forward pulse delay circuit. The first AND circuit is provided for controlling the supply of the output of the clock receiver to the delay monitor. The second AND is provided for controlling the supply of the output of the delay monitor to the forward pulse delay circuit.
摘要翻译：一种时钟同步电路，包括时钟接收器，延迟监视器，正向脉冲延迟电路，反向脉冲延迟电路，驱动器，状态保持部分，控制信号发生电路，第一AND电路和第二AND电路。延迟监视器延迟时钟接收器的输出。正向脉冲延迟电路延迟延迟监视器的输出。反向脉冲延迟电路延迟时钟接收器的输出。驱动器接收反向脉冲延迟电路的输出并输出内部时钟信号。状态保持部控制反向脉冲延迟电路。控制脉冲发生电路初始化正向脉冲延迟电路。第一AND电路用于控制时钟接收器对延迟监视器的输出的供应。第二AND被提供用于控制向正向脉冲延迟电路提供延迟监视器的输出。

46. 发明授权

US6088290A Semiconductor memory device having a power-down mode 失效
标题翻译：具有掉电模式的半导体存储器件
公开(公告)号：US6088290A
公开(公告)日：2000-07-11
申请号：US132644
申请日：1998-08-11
申请人： Hiroyuki Ohtake , Shigeo Ohshima , Takehiro Hasegawa
发明人： Hiroyuki Ohtake , Shigeo Ohshima , Takehiro Hasegawa
IPC分类号： G11C11/413 , G11C7/20 , G11C7/22 , G11C11/407 , G11C11/409 , G11C8/00
CPC分类号： G11C7/22 , G11C7/20
摘要： When a clock enable signal asynchronous with a clock signal is set at a high level, a power-down control circuit sets a power-down signal at a high level to release a power-down mode. When the power-down mode is released, a clock control circuit outputs an internal clock signal such that an output signal of a command decoder can be latched. According to such a constitution, a period of time from the latching of the command after releasing the power-down mode to the time when the command can be transferred will be reduced, and a high-speed operation can be attained.
摘要翻译：当与时钟信号异步的时钟使能信号被设置为高电平时，掉电控制电路将掉电信号设置在高电平以释放掉电模式。当释放掉电模式时，时钟控制电路输出内部时钟信号，使得可以锁存命令解码器的输出信号。根据这样的结构，可以减少在释放掉电模式之后的命令的锁存到命令可以传送的时间段，并且可以实现高速操作。

47. 发明授权

US5949090A MOS TEG structure 失效
标题翻译： MOS TEG结构
公开(公告)号：US5949090A
公开(公告)日：1999-09-07
申请号：US933321
申请日：1997-09-18
申请人： Kiyoaki Iwasa , Shigeo Ohshima
发明人： Kiyoaki Iwasa , Shigeo Ohshima
IPC分类号： G01R31/26 , G01R31/28 , H01L21/66 , H01L21/822 , H01L23/544 , H01L27/04 , H01L23/58
CPC分类号： H01L22/34 , G01R31/2884
摘要： A semiconductor integrated circuit includes a rectangular semiconductor chip having a main surface, a plurality of pads formed in a peripheral portion of the main surface of the semiconductor chip, for connection to external connecting members, a plurality of circuit elements of an integrated circuit formed in an area of the main surface other than an area in which the plurality of pads are formed, and at least one characteristic evaluating circuit element connected to at least one of the plurality of circuit elements of the integrated circuit by sharing an impurity doped region which forms part of the at least one circuit element with the at least one circuit element of the integrated circuit in an area of the main surface other than the peripheral portion in which the plurality of pads are formed.
摘要翻译：半导体集成电路包括具有主表面的矩形半导体芯片，形成在半导体芯片的主表面的周边部分中的多个焊盘，用于连接到外部连接构件，形成为集成电路的多个电路元件除了形成多个焊盘的区域之外的主表面的区域，以及至少一个特征评估电路元件，其通过共享形成的杂质掺杂区域而与集成电路的多个电路元件中的至少一个连接所述至少一个电路元件的一部分与所述集成电路的所述至少一个电路元件在所述主表面的除了形成所述多个焊盘的外围部分之外的区域中。

48. 发明授权

US5841730A Semiconductor memory device having synchronous write driver circuit 失效
标题翻译：具有同步写入驱动电路的半导体存储器件
公开(公告)号：US5841730A
公开(公告)日：1998-11-24
申请号：US790907
申请日：1997-01-29
申请人： Yasuyuki Kai , Katsushi Nagaba , Shigeo Ohshima
发明人： Yasuyuki Kai , Katsushi Nagaba , Shigeo Ohshima
IPC分类号： G11C11/409 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G11C7/1048 , G11C7/1078
摘要： A semiconductor memory device capable of shortening data reading time in a first read cycle after the mode has been changed from a write mode to a read mode while maintaining high-speed cycle time when data is written despite simple structure, the semiconductor memory device having a memory cell array having a plurality of dynamic memory cells, to which data can be written, data line pairs to which data read from the memory cells and data which must be written on the memory cells are transferred, a write driver for driving the data line pairs in accordance with write data supplied from outside when data is written to the memory cells and an equalizing circuit for setting the data line pairs to an intermediate potential whenever the data line pairs are operated by the write driver.
摘要翻译：一种半导体存储器件，其能够在模式已经从写入模式改变为读取模式之后在第一读取周期中缩短数据读取时间，同时在尽可能简单的结构写入数据时保持高速循环时间，半导体存储器件具有存储单元阵列，具有可以写入数据的多个动态存储器单元，从存储单元读取数据的数据线对和必须写入存储单元的数据被传送到其上，用于驱动数据线的写入驱动器当数据被写入存储单元时，根据从外部提供的写入数据成对，以及均衡电路，用于每当数据线对由写入驱动器操作时将数据线对设置为中间电位。

49. 发明授权

US5233564A Multiport memory with test signal generating circuit controlling data transfer from RAM port to SAM port 失效
标题翻译：具有测试信号产生电路的多个存储器控制数据从RAM端口传输到SAM端口
公开(公告)号：US5233564A
公开(公告)日：1993-08-03
申请号：US712701
申请日：1991-06-10
申请人： Shigeo Ohshima , Tatsuo Ikawa
发明人： Shigeo Ohshima , Tatsuo Ikawa
IPC分类号： G11C7/10 , G11C29/00 , G11C29/02 , G11C29/46
CPC分类号： G11C29/46 , G11C29/003 , G11C29/02 , G11C7/1075
摘要： The disclosed semiconductor memory comprises a random access memory port, a serial access memory port, a data transfer gate formed between the two ports, and in particular a test signal generating circuit for generating a test signal to the data transfer gate to close the gate so that data stored in the serial access memory port can be read to outside, without transferring data from the random access memory port to the serial access memory port. Therefore, it is possible to discriminate an erroneous operation caused when data are read from the serial access memory port from that caused when data are transferred from the random access memory port to the serial access memory port.

50. 发明授权

US5138581A Multiport memory 失效
标题翻译：多端口内存
公开(公告)号：US5138581A
公开(公告)日：1992-08-11
申请号：US577361
申请日：1990-09-05
申请人： Shinji Miyamoto , Shigeo Ohshima
发明人： Shinji Miyamoto , Shigeo Ohshima
IPC分类号： G11C11/401 , G11C7/10
CPC分类号： G11C7/1075
摘要： A multiport memory has a RAM port including a memory cell array having a plurality of memory cells arranged in a matrix form, sense amplifier circuit for sensing potential of a bit line after the storage potential has been transferred from the memory cells, restore circuit connected to the bit line for pulling up the potential of the bit line at the predetermined timing after sense operation has been started and a barrier circuit connected between the bit line and the sense amplifier circuit; and a SAM port including a data register, transfer gate and functional means for transferring serial data in the column direction. In this memory, the RAM port is connected to the SAM port by the transfer gate with the bit line directly connected to the data register, and the potentials at the bit line are amplified by the sense amplifier circuit and are directly transferred to the data register.
摘要翻译：多端口存储器具有包括具有以矩阵形式布置的多个存储单元的存储单元阵列的RAM端口，用于在从存储单元传送存储电位之后感测位线的电位的读出放大器电路，恢复电路连接到用于在感测操作之后的预定定时提升位线的电位的位线和连接在位线和读出放大器电路之间的屏障电路; 以及包括数据寄存器，传送门和用于在列方向上传送串行数据的功能装置的SAM端口。在该存储器中，RAM端口通过传输门连接到SAM端口，位线直接连接到数据寄存器，位线上的电位由读出放大器电路放大并直接传输到数据寄存器。

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