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41. 发明授权

US07379320B2 Method for operating an MFIS ferroelectric memory array 有权
标题翻译：用于操作MFIS铁电存储器阵列的方法
公开(公告)号：US07379320B2
公开(公告)日：2008-05-27
申请号：US11262117
申请日：2005-10-28
申请人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
IPC分类号： G11C11/22 , H01L21/8246 , H01L21/8247
CPC分类号： H01L27/1159 , H01L21/84 , H01L27/11502 , H01L27/11585
摘要： An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.
摘要翻译：一种MFIS存储器阵列，具有多个具有连接多个MFIS存储晶体管栅极的字线的MFIS存储晶体管，其中连接到公共字线的所有MFIS存储晶体管具有公共源，每个晶体管漏极用作位输出，以及沿着字线的所有MFIS通道被P +区隔开，并且通过P +区进一步连接到SOI衬底上的P +衬底区域。还提供了在SOI衬底上制造MFIS存储器阵列的方法; 执行一个或多个字线的块擦除的方法以及有选择地编程位的方法。

42. 发明授权

US06819583B2 Ferroelectric resistor non-volatile memory array 失效
标题翻译：铁电电阻非易失性存储器阵列
公开(公告)号：US06819583B2
公开(公告)日：2004-11-16
申请号：US10345726
申请日：2003-01-15
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric thin film resistor memory array is formed on a substrate and includes plural memory cells arranged in an array of rows and columns; wherein each memory cell includes: a FE resistor having a pair of terminals, and a transistor associated with each resistor, wherein each transistor has a gate, a drain and a source, and wherein the drain of each transistor is electrically connected to one terminal of its associated resistor; a word line connected to the gate of each transistor in a row; a programming line connected to each memory cell in a column; and a bit line connected to each memory cell in a column.
摘要翻译：铁基薄膜电阻存储阵列形成在基板上，并且包括以行和列为阵列排列的多个存储单元; 其中每个存储器单元包括：具有一对端子的FE电阻器和与每个电阻器相关联的晶体管，其中每个晶体管具有栅极，漏极和源极，并且其中每个晶体管的漏极电连接到其相关电阻器; 连接到每个晶体管的栅极的字线; 连接到列中的每个存储单元的编程线; 以及连接到列中每个存储单元的位线。

43. 发明授权

US06759250B2 Deposition method for lead germanate ferroelectric structure with multi-layered electrode 失效
标题翻译：具有多层电极的锗酸铅铁电结构沉积方法
公开(公告)号：US06759250B2
公开(公告)日：2004-07-06
申请号：US10196503
申请日：2002-07-15
申请人： Fengyan Zhang , Tingkai Li , Sheng Teng Hsu
发明人： Fengyan Zhang , Tingkai Li , Sheng Teng Hsu
IPC分类号： H01L2100
CPC分类号： H01L28/56 , H01L21/31604 , H01L21/31691 , H01L28/75
摘要： The ferroelectric structure including a Pt/Ir layered electrode used in conjunction with a lead germanate (Pb5Ge3O11) thin film is provided. The electrode exhibits good adhesion to the substrate, and barrier properties resistant to oxygen and lead. Ferroelectric properties are improved, without detriment to the leakage current, by using a thin IrO2 layer formed in situ, during the MOCVD lead germanate (Pb5Ge3O11) thin film process. By using a Pt/Ir electrode, a relatively low MOCVD processing temperature is required to achieve c-axis oriented lead germanate (Pb5Ge3O11) thin film. The temperature range of MOCVD c-axis oriented lead germanate (Pb5Ge3O11) thin film on top of Pt/Ir is 400-500° C. Further, a relatively large nucleation density is obtained, as compared to using single-layer iridium electrode. Therefore, the lead germanate (Pb5Ge3O11) thin film has a smooth surface, a homogeneous microstructure, and homogeneous ferroelectric properties. A method of forming the above-mentioned multi-layered electrode ferroelectric structure is also provided.
摘要翻译：提供了包括与锗酸铅（Pb5Ge3O11）薄膜结合使用的Pt / Ir层叠电极的铁电体结构。该电极对基材表现出良好的粘合性，并且对氧和铅具有阻挡性能。在MOCVD锗酸铅（Pb5Ge3O11）薄膜工艺中，通过使用在原位形成的薄的IrO 2层，铁电性能得到改善，而不损害漏电流。通过使用Pt / Ir电极，需要相对低的MOCVD处理温度来实现c轴取向的锗酸铅（Pb5Ge3O11）薄膜。 Pt / Ir顶部的MOCVD c轴取向锗酸铅（Pb5Ge3O11）薄膜的温度范围为400-500℃。与使用单层铱电极相比，获得了较大的成核密度。因此，锗酸铅（Pb5Ge3O11）薄膜表面光滑，微观组织均匀，铁电性能均匀。还提供了形成上述多层电极铁电体结构体的方法。

44. 发明授权

US06531324B2 MFOS memory transistor & method of fabricating same 失效
公开(公告)号：US06531324B2
公开(公告)日：2003-03-11
申请号：US09820039
申请日：2001-03-28
申请人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
IPC分类号： H01L2100
CPC分类号： H01L29/516 , H01L21/28291 , H01L29/78391
摘要： A ferroelectric transistor gate structure with a ferroelectric gate and passivation sidewalls is provided. The passivation sidewalls serve as an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing passivation insulator material, etching the passivation insulator material using anisotropic plasma etching to form passivation sidewalls, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.

45. 发明授权

US06495378B2 Ferroelastic lead germanate thin film and deposition method 有权
标题翻译：铁硬脂酸铅薄膜和沉积方法
公开(公告)号：US06495378B2
公开(公告)日：2002-12-17
申请号：US09814273
申请日：2001-03-21
申请人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L2100
CPC分类号： H01L21/02197 , C23C16/40 , H01L21/02271 , H01L21/31604 , H01L21/31691
摘要： A Pb3GeO5 phase PGO thin film is provided. This film has ferroelastic properties that make it ideal for many microelectromechanical applications or as decoupling capacitors in high speed multichip modules. This PGO film is uniquely formed in a MOCVD process that permits a thin film, less than 1 mm, of material to be deposited. The process mixes Pd and germanium in a solvent. The solution is heated to form a precursor vapor which is decomposed. The method provides deposition temperatures and pressures. The as-deposited film is also annealed to enhanced the film's ferroelastic characteristics. A ferroelastic capacitor made from the present invention PGO film is also provided.
摘要翻译：提供Pb3GeO5相PGO薄膜。该薄膜具有铁弹性，使其成为许多微机电应用或高速多芯片模块中的去耦电容器的理想选择。该PGO膜在MOCVD工艺中唯一形成，其允许沉积小于1mm的薄膜。该方法将Pd和锗在溶剂中混合。将溶液加热以形成分解的前体蒸汽。该方法提供沉积温度和压力。沉积的膜也被退火以增强膜的铁弹性特征。还提供了由本发明PGO膜制成的铁弹性电容器。

46. 发明授权

US06190925B1 Epitaxially grown lead germanate film and deposition method 有权
标题翻译：外延生长的锗酸铅膜和沉积法
公开(公告)号：US06190925B1
公开(公告)日：2001-02-20
申请号：US09302272
申请日：1999-04-28
申请人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L2100
CPC分类号： H01L21/31604 , C23C16/40 , H01L21/31691 , Y10S438/933
摘要： The present invention provides a substantially single crystal PGO film with optimal the ferroelectric properties. The PGO film and adjacent electrodes are epitaxially grown to minimize mismatch between the structures. MOCVD deposition methods and RTP annealing procedures permit a PGO film to be epitaxially grown in commercial fabrication processes. These epitaxial ferroelectric have application in FeRAM memory devices. The present invention deposition method epitaxially grows ferroelectric Pb5Ge3O11 thin films along with c-axis orientation.
摘要翻译：本发明提供了具有最佳铁电性能的基本单晶PGO膜。 PGO膜和相邻电极被外延生长以最小化结构之间的失配。 MOCVD沉积方法和RTP退火程序允许PGO膜在商业制造工艺中外延生长。这些外延铁电体已经应用于FeRAM存储器件中。本发明沉积方法外延生长铁电Pb5Ge3O11薄膜以及c轴取向。

47. 发明授权

US07112837B2 MFIS ferroelectric memory array 有权
标题翻译： MFIS铁电存储器阵列
公开(公告)号：US07112837B2
公开(公告)日：2006-09-26
申请号：US11262545
申请日：2005-10-28
申请人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
IPC分类号： H01L29/76
CPC分类号： H01L27/1159 , H01L21/84 , H01L27/11502 , H01L27/11585
摘要： An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.
摘要翻译：一种MFIS存储器阵列，具有多个具有连接多个MFIS存储晶体管栅极的字线的MFIS存储晶体管，其中连接到公共字线的所有MFIS存储晶体管具有公共源，每个晶体管漏极用作位输出，以及沿着字线的所有MFIS通道被P +区隔开，并且通过P +区进一步连接到SOI衬底上的P +衬底区域。还提供了在SOI衬底上制造MFIS存储器阵列的方法; 执行一个或多个字线的块擦除的方法以及有选择地编程位的方法。

48. 发明授权

US06991942B1 MFIS ferroelectric memory array on SOI and method of making same 失效
标题翻译： SOI上的MFIS铁电存储阵列及其制作方法
公开(公告)号：US06991942B1
公开(公告)日：2006-01-31
申请号：US10953912
申请日：2004-09-28
申请人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
IPC分类号： H01L21/00
CPC分类号： H01L27/1159 , H01L21/84 , H01L27/11502 , H01L27/11585
摘要： An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.
摘要翻译：一种MFIS存储器阵列，具有多个具有连接多个MFIS存储晶体管栅极的字线的MFIS存储晶体管，其中连接到公共字线的所有MFIS存储晶体管具有公共源，每个晶体管漏极用作位输出，以及沿着字线的所有MFIS通道被P +区隔开，并且通过P +区进一步连接到SOI衬底上的P +衬底区域。还提供了在SOI衬底上制造MFIS存储器阵列的方法; 执行一个或多个字线的块擦除的方法以及有选择地编程位的方法。

49. 发明授权

US06737693B2 Ferroelastic integrated circuit device 失效
标题翻译：铁磁集成电路器件
公开(公告)号：US06737693B2
公开(公告)日：2004-05-18
申请号：US10412890
申请日：2003-04-14
申请人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L2976
CPC分类号： H01L21/02197 , C23C16/40 , H01L21/02271 , H01L21/31604 , H01L21/31691
摘要： A Pb3GeO5 phase PGO thin film is provided. This film has ferroelastic properties that make it ideal for many microelectromechanical applications or as decoupling capacitors in high speed multichip modules. This PGO film is uniquely formed in a MOCVD process that permits a thin film, less than 1 mm, of material to be deposited. The process mixes Pd and germanium in a solvent. The solution is heated to form a precursor vapor which is decomposed. The method provides deposition temperatures and pressures. The as-deposited film is also annealed to enhanced the film's ferroelastic characteristics. A ferroelastic capacitor made from the present invention PGO film is also provided.
摘要翻译：提供Pb3GeO5相PGO薄膜。该薄膜具有铁弹性，使其成为许多微机电应用或高速多芯片模块中的去耦电容器的理想选择。该PGO膜在MOCVD工艺中唯一形成，其允许沉积小于1mm的薄膜。该方法将Pd和锗在溶剂中混合。将溶液加热以形成分解的前体蒸汽。该方法提供沉积温度和压力。沉积的膜也被退火以增强膜的铁弹性特征。还提供了由本发明PGO膜制成的铁弹性电容器。

50. 发明授权

US06703655B2 Ferroelectric memory transistor 失效
标题翻译：铁电存储晶体管
公开(公告)号：US06703655B2
公开(公告)日：2004-03-09
申请号：US10385038
申请日：2003-03-10
申请人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
IPC分类号： H01L2976
CPC分类号： G11C11/22 , H01L21/28291 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L27/11502 , H01L29/78391
摘要： A ferroelectric memory transistor includes a substrate having active regions therein; a gate stack, including: a high-k insulator element, including a high-k cup and a high-k cap; a ferroelectric element, wherein said ferroelectric element is encapsulated within said high-k insulator element; and a top electrode located on a top portion of said high-k insulator; a passivation oxide layer located over the substrate and gate stack; and metalizations to form contacts to the active regions and the gate stack. A method of forming a ferroelectric memory transistor includes preparing a substrate, including forming active regions and an oxide device isolation region; forming a gate placeholder structure in a gate region; removing the gate placeholder structure forming a gate void in the gate region; depositing a high-k insulator layer over the structure and in the gate void to from a high-k cup; filling the high-k cup with a ferroelectric material to form a ferroelectric element; depositing a high-k upper insulator layer and removing excess high-k material to form a high-k cap over the ferroelectric element; depositing a top electrode over the high-k cap to form a gate electrode and gate stack; depositing a layer of passivation oxide over the structure; etching the passivation oxide to from contact vias to the active regions and the gate stack; and metallizing the structure to complete the ferroelectric memory transistor.
摘要翻译：铁电存储晶体管包括其中具有有源区的衬底; 包括：高k绝缘体元件，包括高k杯和高k帽; 铁电元件，其中所述铁电元件封装在所述高k绝缘体元件内; 以及位于所述高k绝缘体的顶部上的顶电极; 位于衬底和栅极叠层上方的钝化氧化物层; 以及金属化以形成与有源区和栅叠层的接触。形成铁电存储晶体管的方法包括：制备基片，包括形成有源区和氧化物器件隔离区; 在栅极区域形成栅极占位符结构; 去除在栅极区域中形成栅极空隙的栅极占位符结构; 在结构上和栅极空隙中沉积高k绝缘体层以从高k杯沉积; 用铁电材料填充高k杯以形成铁电元件; 沉积高k上绝缘体层并去除多余的高k材料以在铁电元件上形成高k帽; 在顶部电极上沉积高k帽以形成栅电极和栅叠层; 在结构上沉积一层钝化氧化物; 将钝化氧化物从接触孔蚀刻到有源区和栅叠层; 并且对结构进行金属化以完成铁电存储晶体管。

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