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41. 发明授权

US08638197B2 Two way remote control 有权
标题翻译：双向遥控
公开(公告)号：US08638197B2
公开(公告)日：2014-01-28
申请号：US13550271
申请日：2012-07-16
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： G05B11/01
CPC分类号： G08C17/02 , G08C2201/30
摘要： A target device including a first tuner to output first signals from a first channel to an output device of the target device, a second tuner to selectively output second signals from a second channel to a remote control device, and an autonegotiation module to exchange data with the remote control device. The remote control device is configured to control the target device. The data exchanged with the remote control device relates to capabilities of at least one of the target device and the remote control device. The data includes at least one of an output resolution of the target device, a display size of the remote control device, a display resolution of the remote control device, and a processing power of the remote control device. The second tuner outputs the second signals to the remote control device based on the data exchanged with the remote control device.
摘要翻译：一种目标设备，包括：第一调谐器，用于将第一信号从第一通道输出到目标设备的输出设备;第二调谐器，用于选择性地将第二信号从第二通道输出到远程控制设备;以及自动协商模块，用于与遥控设备。远程控制设备被配置为控制目标设备。与远程控制设备交换的数据涉及目标设备和远程控制设备中的至少一个的能力。数据包括目标设备的输出分辨率，遥控设备的显示尺寸，遥控设备的显示分辨率和遥控设备的处理能力中的至少一个。第二调谐器基于与遥控装置交换的数据将第二信号输出到遥控装置。

42. 发明授权

US08619571B1 Chip-to-chip interface for 1000base-T gigabit physical layer device 有权
标题翻译： 1000base-T千兆物理层设备的芯片到芯片接口
公开(公告)号：US08619571B1
公开(公告)日：2013-12-31
申请号：US13230769
申请日：2011-09-12
申请人： Sehat Sutardja , William Lo
发明人： Sehat Sutardja , William Lo
IPC分类号： H04L12/26
CPC分类号： H04L47/25 , H04J3/18 , H04L12/2874 , H04L25/0262 , H04L49/3054 , H04L49/351 , H04L69/24
摘要： A physical layer interface including an auto-negotiation circuit configured to negotiate a first data transmission rate with a network client; a transceiver configured to communicate with the network client at the first data transmission rate; and a serializer interface configured to communicate with a media access controller at a second data transmission rate that is different than the first data transmission rate. The serializer interface includes a transmitter configured to replicate data received from the network client in response to the first data transmission rate being lower than the second data transmission rate.
摘要翻译：一种物理层接口，包括被配置为与网络客户端协商第一数据传输速率的自动协商电路; 收发器，被配置为以所述第一数据传输速率与所述网络客户端进行通信; 以及串行接口，被配置为以与第一数据传输速率不同的第二数据传输速率与媒体接入控制器进行通信。串行器接口包括发射机，其被配置为响应于第一数据传输速率低于第二数据传输速率来复制从网络客户端接收的数据。

43. 发明授权

US08525317B1 Integrated chip package having intermediate substrate with capacitor 有权
标题翻译：集成芯片封装，具有带电容器的中间基板
公开(公告)号：US08525317B1
公开(公告)日：2013-09-03
申请号：US11133358
申请日：2005-05-20
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： H01L23/02
CPC分类号： H01L25/162 , H01L23/3675 , H01L23/49833 , H01L24/48 , H01L2224/16145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated chip package includes at least one semiconductor chip. The at least one semiconductor chip includes a first surface and a second surface. The integrated chip package includes an intermediate substrate. The intermediate substrate is electrically coupled via conductive bumps to the first surface of the at least one semiconductor chip. The intermediate substrate includes at least one capacitor electrically coupled to the at least one semiconductor chip. The at least one capacitor includes a trench capacitor. The integrated chip package includes a package substrate. The package substrate includes a first surface electrically coupled to the intermediate substrate via a plurality of bonding wires.
摘要翻译：集成芯片封装包括至少一个半导体芯片。所述至少一个半导体芯片包括第一表面和第二表面。集成芯片封装包括中间基板。中间衬底通过导电凸块电耦合到至少一个半导体芯片的第一表面。中间衬底包括电耦合到至少一个半导体芯片的至少一个电容器。所述至少一个电容器包括沟槽电容器。集成芯片封装包括封装基板。封装衬底包括经由多个接合线电耦合到中间衬底的第一表面。

44. 发明授权

US08503961B1 Active resistive summer for a transformer hybrid 有权
标题翻译：用于变压器混合动态的有源电阻夏季
公开(公告)号：US08503961B1
公开(公告)日：2013-08-06
申请号：US13279873
申请日：2011-10-24
申请人： Pierte Roo , Sehat Sutardja
发明人： Pierte Roo , Sehat Sutardja
IPC分类号： H04B1/10 , H04B3/20 , H04B1/38
CPC分类号： H04L1/0041 , H04B1/581 , H04B3/23 , H04B3/32
摘要： A system includes a transceiver configured to receive a composite signal. The composite signal is a composite of a transmit signal and a receive signal. A replica transmitter is configured to generate a replica transmit signal based on the transmit signal. A transmit canceller is configured to recover the receive signal at least in part by resistively summing the composite signal and the replica transmit signal.
摘要翻译：系统包括被配置为接收复合信号的收发器。复合信号是发射信号和接收信号的组合。复制发射机被配置为基于发射信号生成复制发射信号。发送消除器被配置为至少部分地通过对复合信号和复制发送信号进行电阻求和来恢复接收信号。

45. 发明授权

US08462569B1 Memory repair system and method 有权
标题翻译：内存修复系统和方法
公开(公告)号：US08462569B1
公开(公告)日：2013-06-11
申请号：US13544482
申请日：2012-07-09
申请人： Albert Wu , Sehat Sutardja
发明人： Albert Wu , Sehat Sutardja
IPC分类号： G11C7/00
CPC分类号： G06F11/0793 , G06F11/073 , G11C29/789
摘要： Systems and methods for operating an integrated circuit. The method includes: storing data in one or more of a plurality of locations in a memory module, wherein each location in the memory module has a corresponding memory address; storing a memory address of each location in the memory module detected to be defective in a memory repair module; detecting one or more locations in the memory module that are defective, locating one or more redundant memory elements in the memory module, and storing information in the memory repair database, the information associating the memory address of each location in the memory detected to be defective with the redundant memory elements; and physically remapping the memory addresses to a corresponding redundant memory element.
摘要翻译：用于操作集成电路的系统和方法。该方法包括：将数据存储在存储器模块中的多个位置中的一个或多个位置，其中存储器模块中的每个位置具有对应的存储器地址; 将检测到的有缺陷的存储器模块中的每个位置的存储器地址存储在存储器修复模块中; 检测所述存储器模块中的一个或多个位置是有缺陷的，将一个或多个冗余存储器元件定位在所述存储器模块中，以及将信息存储在所述存储器修复数据库中，所述信息将检测到的所述存储器中的每个位置的存储器地址与缺陷相关联与冗余存储元件; 并将存储器地址物理地重映射到相应的冗余存储器元件。

46. 发明授权

US08412878B2 Combined mobile device and solid state disk with a shared memory architecture 有权
标题翻译：组合移动设备和固态磁盘与共享内存架构
公开(公告)号：US08412878B2
公开(公告)日：2013-04-02
申请号：US12501728
申请日：2009-07-13
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0246 , G06F12/023 , Y02D10/13
摘要： A mobile device including a system-on-chip, which includes a mobile device control module to execute application programs for the mobile device, a solid-state disk (SSD) control module to control SSD operations, a random access memory (RAM) control module to store both SSD-related data and mobile device-related data in a single RAM, and a nonvolatile (NV) memory control module to control reading from and writing to the NV memory array. Data in the single RAM is stored into the NV memory array during an idle mode. The single RAM is powered down during the idle mode after the data in the single RAM has been stored into the NV memory array. The stored data in the NV memory array is loaded into the single RAM during a re-start mode.
摘要翻译：一种移动设备，包括片上系统，其包括用于执行移动设备的应用程序的移动设备控制模块，用于控制SSD操作的固态盘（SSD）控制模块，随机存取存储器（RAM）控制模块，用于将SSD相关数据和移动设备相关数据存储在单个RAM中;以及非易失性（NV）存储器控制模块，用于控制对NV存储器阵列的读取和写入。在空闲模式下，单个RAM中的数据被存储到NV存储器阵列中。在单个RAM中的数据已经存储到NV存储器阵列中之后，单个RAM在空闲模式下关闭电源。 NV存储器阵列中存储的数据在重新启动模式下被加载到单个RAM中。

47. 发明申请

US20120326282A1 METHODS AND ARRANGEMENTS RELATING TO SEMICONDUCTOR PACKAGES INCLUDING MULTI-MEMORY DIES 有权
标题翻译：与包含多存储器件的半导体封装相关的方法和布置
公开(公告)号：US20120326282A1
公开(公告)日：2012-12-27
申请号：US13532444
申请日：2012-06-25
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： H01L25/065 , H01L21/98
CPC分类号： H01L24/43 , G11C5/063 , H01L23/3128 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/105 , H01L25/16 , H01L25/18 , H01L25/50 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/06156 , H01L2224/131 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/43 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/49175 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06562 , H01L2225/06589 , H01L2225/1052 , H01L2225/1058 , H01L2924/00014 , H01L2924/12042 , H01L2924/1434 , H01L2924/1436 , H01L2924/15311 , H01L2924/15321 , H01L2924/014 , H01L2924/00 , H01L2924/00012 , H01L2224/05552 , H01L2224/45099 , H01L2224/05599
摘要： Embodiments provide a method comprising providing a multi-memory die that comprises multiple individual memory dies. Each of the individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies. The multi-memory die is created by singulating the wafer of semiconductor material into memory dies where at least one of the memory dies is a multi-memory die that includes multiple individual memory dies that are still physically connected together. The method further comprises coupling a semiconductor die to the multi-memory die.
摘要翻译：实施例提供了一种方法，包括提供包括多个单独存储器管芯的多存储器管芯。各个存储器管芯在存储器管芯的制造期间被定义为半导体材料晶片内的单个存储器管芯。多存储器管芯是通过将半导体材料的晶片分成存储器管芯而形成的，其中至少一个存储器管芯是包括仍然物理连接在一起的多个独立存储器管芯的多存储器管芯。该方法还包括将半导体管芯耦合到多存储器管芯。

48. 发明申请

US20120313692A1 SUPER-HIGH-VOLTAGE RESISTOR ON SILICON 审中-公开
标题翻译：硅超级高压电阻
公开(公告)号：US20120313692A1
公开(公告)日：2012-12-13
申请号：US13467648
申请日：2012-05-09
申请人： Sehat Sutardja , Ravishanker Krishnamoorthy , Siew Yong Chui
发明人： Sehat Sutardja , Ravishanker Krishnamoorthy , Siew Yong Chui
IPC分类号： G05F3/02
CPC分类号： H01L28/20 , H01L27/0676 , H01L27/0794
摘要： An integrated circuit (IC) including a first layer of a conducting material; a second layer of an insulating material, where the second layer has a first side arranged adjacent to the first layer, and a second side; and a substrate arranged adjacent to the second side of the second layer. A first well arranged in the substrate. The first well is adjacent to the second side of the second layer. The substrate and the first well have opposite doping.
摘要翻译：一种包括导电材料的第一层的集成电路（IC）绝缘材料的第二层，其中所述第二层具有邻近所述第一层设置的第一侧和第二侧; 以及布置成与第二层的第二侧相邻的衬底。布置在基板中的第一阱。第一井与第二层的第二侧相邻。衬底和第一阱具有相反的掺杂。

49. 发明申请

US20120192001A1 COMPUTER WITH LOW-POWER SECONDARY PROCESSOR AND SECONDARY DISPLAY 有权
标题翻译：具有低功率二次加工器和二次显示器的计算机
公开(公告)号：US20120192001A1
公开(公告)日：2012-07-26
申请号：US13437490
申请日：2012-04-02
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： G06F1/32
CPC分类号： G06F1/1647 , G06F1/1616 , G06F1/1692 , G06F1/3203 , G06F1/3287 , G06F1/3293 , Y02D10/122 , Y02D10/171 , Y02D50/20
摘要： A device operable in each of active and inactive modes includes first and second processors. The first processor performs, in accordance with a first power level, both wireless and non-wireless network processing. A second processor performs wireless network processing in accordance with a second power level. While the device is operating in the active mode: the first processor and the first display are powered up; the first display displays a result of the wireless network processing or the non-wireless network processing by the first processor; and the second processor and the second display are powered down. While the device is operating in the inactive mode: the first processor and the first display are powered down; the second processor and the second display are powered up; and the second display displays a result of the wireless network related processing by the second processor.
摘要翻译：可在每个活动模式和非活动模式中操作的设备包括第一和第二处理器。第一处理器根据第一功率电平执行无线和非无线网络处理。第二处理器根据第二功率级执行无线网络处理。当设备工作在主动模式时：第一个处理器和第一个显示器通电; 第一显示器显示第一处理器的无线网络处理或非无线网络处理的结果; 并且第二处理器和第二显示器被断电。当设备处于非活动模式时：第一个处理器和第一个显示器被关闭; 第二处理器和第二显示器通电; 并且第二显示器显示由第二处理器进行的无线网络相关处理的结果。

50. 发明授权

US08217727B1 Slew rate edge enhancer 有权
标题翻译：压摆率边缘增强器
公开(公告)号：US08217727B1
公开(公告)日：2012-07-10
申请号：US12686773
申请日：2010-01-13
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： H03B1/00
CPC分类号： H03K5/12 , H03B5/1215 , H03B5/1228 , H03B5/124 , H03B28/00
摘要： A slew rate enhancing system is disclosed. The slew rate enhancing system includes a first switch and a second switch each having a control terminal, a first terminal, and a second terminal. The first terminals of the first and second switches receive a first signal of a differential signal pair. The control terminals of the first and second switches receive a second signal of the differential signal pair. A first output is connected to the second terminals of the first and second switches.
摘要翻译：公开了一种压摆率增强系统。压摆率增强系统包括第一开关和第二开关，每个具有控制端子，第一端子和第二端子。第一和第二开关的第一端接收差分信号对的第一信号。第一和第二开关的控制端接收差分信号对的第二信号。第一输出连接到第一和第二开关的第二端子。

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