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41. 发明授权

US07432162B2 Semiconductor device with substantial driving current and decreased junction leakage current 失效
标题翻译：半导体器件具有实质的驱动电流和降低的结漏电流
公开(公告)号：US07432162B2
公开(公告)日：2008-10-07
申请号：US11480866
申请日：2006-07-06
申请人： Sung Woong Chung , Sang Don Lee
发明人： Sung Woong Chung , Sang Don Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/78642 , H01L29/42376 , H01L29/66621
摘要： The semiconductor device includes an active region, a stepped recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The stepped recess channel region is formed in the active region. The vertical silicon-on-insulator (SOI) channel structures are disposed at sidewalls of both device isolation structures in a longitudinal direction of a gate region. The gate insulating film is disposed over the active region including the stepped recess channel region. The gate structure is disposed over the stepped recess channel region of the gate region.
摘要翻译：半导体器件包括有源区，包括垂直沟道结构的阶梯形凹槽沟道区，栅极绝缘膜和栅极结构。有源区由半导体衬底中形成的器件隔离结构限定。在有源区域中形成阶梯状凹槽沟道区域。垂直绝缘体上硅（SOI）通道结构在栅极区域的纵向方向上设置在两个器件隔离结构的侧壁处。栅极绝缘膜设置在包括阶梯式凹槽沟道区域的有源区域之上。栅极结构设置在栅极区域的阶梯状凹槽沟道区域的上方。

42. 发明授权

US07365400B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07365400B2
公开(公告)日：2008-04-29
申请号：US11219795
申请日：2005-09-07
申请人： Sang Don Lee
发明人： Sang Don Lee
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L21/28123 , H01L21/28061 , H01L21/28247 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing semiconductor device employs an EXTIGATE structure. In accordance with the method, a predetermined thickness of the device isolation film is etched to form a recess. The recess is then filled with a second nitride film. A stacked structure of a barrier metal film, a metal layer and a third nitride film on the second nitride film and the polysilicon film are formed on the entire surface and the etched via a photoetching process to form a gate electrode. An insulating film spacer is deposited on a sidewall of the gate electrode. The exposed portion of the polysilicon film uses the third nitride film pattern and the insulating film spacer as a mask to form a polysilicon film pattern and an oxide film on a sidewall of the polysilicon film pattern.
摘要翻译：半导体器件的制造方法采用EXTIGATE结构。根据该方法，对器件隔离膜的预定厚度进行蚀刻以形成凹陷。然后用第二氮化物膜填充凹部。在整个表面上形成第二氮化物膜和多晶硅膜上的阻挡金属膜，金属层和第三氮化物膜的叠层结构，并通过光刻工艺蚀刻以形成栅电极。绝缘膜间隔物沉积在栅电极的侧壁上。多晶硅膜的暴露部分使用第三氮化物膜图案和绝缘膜间隔物作为掩模，以在多晶硅膜图案的侧壁上形成多晶硅膜图案和氧化物膜。

43. 发明申请

US20080057634A1 Method For Forming Semiconductor Device 失效
标题翻译：形成半导体器件的方法
公开(公告)号：US20080057634A1
公开(公告)日：2008-03-06
申请号：US11770628
申请日：2007-06-28
申请人： Sang Don Lee
发明人： Sang Don Lee
IPC分类号： H01L21/84 , H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/66818
摘要： A method for forming a semiconductor device of the present invention solves problems in a process for forming a fin type gate including a recess region, such as, a complicated process, low production margin, and difficulty in forming an accurate fin shape. In a process for forming an isolation dielectric film defining an active region, a nitride film pattern is formed in such a manner that the size of the nitride film is adjusted according to line width of a fin portion in a fin type active region formed in a subsequent process step, and an isolation dielectric film is formed in every region except for the nitride film pattern of a semiconductor substrate. Then, a recess is etched, and the isolation dielectric film is removed from a region where the line width of the nitride film pattern was reduced to a certain degree. Consequently, a process margin for forming a fin type active region is increased, and the shape of a fin shaped portion can be adjusted accurately, which together contribute to improved electrical properties in the semiconductor devices.
摘要翻译：本发明的半导体装置的形成方法解决了形成包括凹陷区域的翅片型浇口的工艺，复杂的工艺，低的生产裕度以及难以形成精确的翅片形状的问题。在形成限定有源区的隔离电介质膜的工艺中，以如下方式形成氮化膜图案：使氮化膜的尺寸根据在随后的工艺步骤，并且除了半导体衬底的氮化物膜图案之外的每个区域中形成隔离电介质膜。然后，蚀刻凹部，从氮化膜图案的线宽减小到一定程度的区域去除隔离电介质膜。因此，用于形成翅片型有源区的工艺余量增加，并且可以精确地调节翅片形状部分的形状，这一起有助于改善半导体器件中的电性能。

44. 发明授权

US07338850B2 Method for manufacturing device isolation film of semiconductor device 有权
标题翻译：制造半导体器件的器件隔离膜的方法
公开(公告)号：US07338850B2
公开(公告)日：2008-03-04
申请号：US10998967
申请日：2004-11-30
申请人： Sang Don Lee
发明人： Sang Don Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/76229 , H01L21/823878 , Y10S438/954
摘要： A method for manufacturing device isolation film of semiconductor device is disclosed. The method utilizes a plasma oxidation of a liner nitride film exposed by etching a liner oxide the film in peripheral region prior to the formation of device isolation film to prevent the generation of a electron trap which causes trapping of electrons at the interface of the oxide film and the nitride film resulting in a HEIP phenomenon.
摘要翻译：公开了半导体器件的器件隔离膜的制造方法。该方法利用在形成器件隔离膜之前通过蚀刻衬底氧化膜外围区域的衬底氮化物膜的等离子体氧化，以防止产生电子阱，该电子阱在氧化物膜的界面处捕获电子并且氮化物膜导致HEIP现象。

45. 发明申请

US20070252198A1 Semiconductor device having a fin channel transistor 审中-公开
标题翻译：具有鳍状沟道晶体管的半导体器件
公开(公告)号：US20070252198A1
公开(公告)日：2007-11-01
申请号：US11529355
申请日：2006-09-29
申请人： Sung Woong Chung , Sang Don Lee
发明人： Sung Woong Chung , Sang Don Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7851 , H01L27/10826 , H01L27/10873 , H01L27/10879 , H01L29/0653 , H01L29/66795
摘要： The semiconductor device includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower part of sidewalls thereof. The semiconductor device additionally has a fin channel region protruded over the device isolation structure in a longitudinal direction of a gate region; a gate insulating film formed over the semiconductor substrate including the protruded fin channel region; and a gate electrode formed over the gate insulating film to fill up the protruded fin channel region.
摘要翻译：半导体器件包括形成在半导体衬底中的器件隔离结构，以限定在其侧壁的下部具有凹陷区域的有源区。半导体器件还具有在栅极区域的纵向方向上在器件隔离结构上突出的鳍状沟道区域; 形成在所述半导体衬底上的栅极绝缘膜，所述栅极绝缘膜包括所述突出的鳍状沟道区域; 以及形成在所述栅极绝缘膜上方以填充所述突出的鳍状沟道区域的栅电极。

46. 发明申请

US20050280113A1 Semiconductor device capable of threshold voltage adjustment by applying an external voltage 失效
标题翻译：能够通过施加外部电压来阈值电压调节的半导体器件
公开(公告)号：US20050280113A1
公开(公告)日：2005-12-22
申请号：US11008363
申请日：2004-12-09
申请人： Yil Kim , Jun Hee Cho , Sung Eon Park , Jin Hong Ahn , Sang Don Lee
发明人： Yil Kim , Jun Hee Cho , Sung Eon Park , Jin Hong Ahn , Sang Don Lee
IPC分类号： H01L21/3065 , H01L21/308 , H01L21/311 , H01L21/336 , H01L21/762 , H01L21/763 , H01L21/764 , H01L21/765 , H01L21/8234 , H01L21/8242 , H01L27/02 , H01L29/00 , H01L29/06 , H01L29/78
CPC分类号： H01L29/7831 , H01L21/3065 , H01L21/3086 , H01L21/76232 , H01L21/763 , H01L21/764 , H01L21/765 , H01L21/823412 , H01L21/823481 , H01L27/0214 , H01L27/10873 , H01L29/0657 , H01L29/66575 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surface of the active region on the side near the device isolation film. An insulating film is formed on the laterally etched portion of the silicon substrate. A conductive electrode is formed on the insulating film, through which an external voltage is applied to adjust a threshold voltage. The device isolation film is formed on the conductive electrode. None or some pockets of vacant cavity is present between the device isolation film and the conductive electrode.
摘要翻译：半导体器件具有硅衬底，其中在两个器件隔离膜之间形成有源区，并且在有源区的表面上形成栅极。硅衬底在靠近器件隔离膜的一侧上的有源区的表面下方的有源区中具有横向蚀刻的部分。绝缘膜形成在硅衬底的横向蚀刻部分上。在绝缘膜上形成导电电极，施加外部电压以调整阈值电压。器件隔离膜形成在导电电极上。在器件隔离膜和导电电极之间不存在或存在一些空穴腔。

47. 发明授权

US06579755B2 High dielectric capacitor and method of manufacturing the same 有权
标题翻译：高介电电容器及其制造方法
公开(公告)号：US06579755B2
公开(公告)日：2003-06-17
申请号：US09855973
申请日：2001-05-15
申请人： You Sung Kim , Sang Don Lee
发明人： You Sung Kim , Sang Don Lee
IPC分类号： H01L2100
CPC分类号： H01L28/55
摘要： A capacitor having a storage electrode and a plate electrode, wherein both are made of metal or metal oxide, a high dielectric film formed between the electrodes, and a method of manufacturing the same. A diffusion prevention film is found at the side of the storage electrode and on the plate electrode. Therefore, the invention prevents deterioration of the property in the dielectric film due to penetration of hydrogen ions during a subsequent thermal process thereby improving the reliability of a device.
摘要翻译：一种具有存储电极和平板电极的电容器及其制造方法，其特征在于，金属或金属氧化物均为双电极形成的高电介质膜。在存储电极的侧面和板极上发现扩散防止膜。因此，本发明可防止在后续热处理过程中由于氢离子渗透导致的电介质膜性能的劣化，从而提高了器件的可靠性。

48. 发明授权

US08587369B2 Down-converting voltage generating circuit 有权
标题翻译：下变频电压发生电路
公开(公告)号：US08587369B2
公开(公告)日：2013-11-19
申请号：US13339034
申请日：2011-12-28
申请人： Chae Kyu Jang , Jong Hyun Wang , Sang Don Lee
发明人： Chae Kyu Jang , Jong Hyun Wang , Sang Don Lee
IPC分类号： G05F3/16 , G05F3/24
CPC分类号： G05F1/56
摘要： A down-converting voltage generating circuit includes a reference voltage providing unit, an initial setting unit, a driving unit, and a driving force control unit. The reference voltage providing unit provides a reference voltage to a first node. The initial setting unit drops a voltage level of the first node to substantially a level of a ground voltage when an initial setting signal is activated. The driving unit drives a down-converted voltage derived from an external voltage in response to the voltage level of the first node. The driving force control unit is connected to the driving unit, and controls a driving force for driving the down-converted voltage of the driving unit in response to the initial setting signal.
摘要翻译：下变频电压发生电路包括基准电压提供单元，初始设定单元，驱动单元和驱动力控制单元。参考电压提供单元向第一节点提供参考电压。当初始设置信号被激活时，初始设置单元将第一节点的电压电平降低到接地电压的大致水平。驱动单元驱动响应于第一节点的电压电平从外部电压导出的下变频电压。驱动力控制单元连接到驱动单元，并且响应于初始设置信号控制用于驱动驱动单元的下变频电压的驱动力。

49. 发明授权

US08389364B2 Method of fabricating a transistor 有权
标题翻译：制造晶体管的方法
公开(公告)号：US08389364B2
公开(公告)日：2013-03-05
申请号：US13196606
申请日：2011-08-02
申请人： Sang Don Lee
发明人： Sang Don Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/088 , H01L21/823412 , H01L21/823456 , H01L21/823481 , H01L27/105 , H01L27/10876 , H01L27/10879 , H01L27/10894 , H01L29/66795 , H01L29/7851
摘要： A method of fabricating a saddle-fin transistor may include: forming a buffer oxide film and a hard mask oxide film over a semiconductor substrate; etching the buffer oxide film, the hard mask oxide film and the semiconductor substrate corresponding to a mask pattern to form a trench corresponding to a gate electrode and a fin region; oxidizing the exposed semiconductor substrate in the trench to form a gate oxide film; depositing a gate lower electrode in the trench; and depositing a gate upper electrode over the gate lower electrode to fill the trench.
摘要翻译：制造鞍形鳍式晶体管的方法可以包括：在半导体衬底上形成缓冲氧化膜和硬掩模氧化膜; 蚀刻缓冲氧化膜，硬掩模氧化物膜和对应于掩模图案的半导体衬底，以形成对应于栅电极和鳍区的沟槽; 氧化暴露的沟槽中的半导体衬底以形成栅氧化膜; 在沟槽中沉积栅极下电极; 以及在所述栅极下电极上沉积栅极上电极以填充所述沟槽。

50. 发明授权

US08357572B2 Method of manufacturing semiconductor device with recess and Fin structure 有权
标题翻译：具有凹槽和鳍结构的半导体器件的制造方法
公开(公告)号：US08357572B2
公开(公告)日：2013-01-22
申请号：US13360194
申请日：2012-01-27
申请人： Sang Don Lee , Sung Woong Chung
发明人： Sang Don Lee , Sung Woong Chung
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L21/823437 , H01L29/4236 , H01L29/66621 , H01L29/7851
摘要： The semiconductor device includes an active region, a recess, a Fin channel region, a gate insulating film, and a gate electrode. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess is formed by etching the active region and its neighboring device isolation structure using an island shaped recess gate mask as an etching mask. The Fin channel region is formed on the semiconductor substrate at a lower part of the recess. The gate insulating film is formed over the active region including the Fin channel region and the recess. The gate electrode is formed over the gate insulating film to fill up the Fin channel region and the recess.
摘要翻译：半导体器件包括有源区，凹槽，Fin沟道区，栅极绝缘膜和栅电极。有源区由半导体衬底中形成的器件隔离结构限定。通过使用岛状凹陷栅极掩模作为蚀刻掩模来蚀刻有源区及其邻近的器件隔离结构来形成凹部。鳍状沟道区在凹部的下部形成在半导体衬底上。栅极绝缘膜形成在包括鳍状沟道区域和凹部的有源区域上。栅电极形成在栅极绝缘膜上，以填充鳍沟道区域和凹槽。

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