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41. 发明专利

DE60107743T2 未知
公开(公告)号：DE60107743T2
公开(公告)日：2005-12-08
申请号：DE60107743
申请日：2001-03-16
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM KYU-HYOUN
IPC分类号： G11C11/407 , G11C7/00 , G11C7/10 , G11C8/18 , H03K5/04 , H03K5/156 , H03L7/00 , H03L7/07 , H03L7/08 , H03L7/081 , H03L7/087
摘要： A signal processing circuit includes a first delay locked loop (DLL) circuit that generates a first intermediate output signal in response to an input signal and a phase difference between a leading edge of a reference signal and a leading edge of a feedback signal and a second DLL circuit that generates a second intermediate output signal in response to the input signal and a phase difference between a trailing edge of the reference signal and a trailing edge of the feedback signal. Because the first and second intermediate output signals are based on the phase difference between the reference signal and the leading and trailing edges of a feedback signal, respectively, and the first and second intermediate output signals are not derived from the reference signal, the jitter that may be introduced into the first and second intermediate output signals may be reduced.

42. 发明专利

DE10125723C2 未知
公开(公告)号：DE10125723C2
公开(公告)日：2003-11-13
申请号：DE10125723
申请日：2001-05-18
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM KYU-HYOUN
IPC分类号： H03K5/13 , H03K5/156 , H03L7/081 , H03K5/135 , G05F1/00
摘要： A delay locked loop circuit having a duty cycle correction function and a delay locking method are provided. The delay locked loop circuit includes a delaying portion for generating a first output signal by uniformly delaying an input first clock signal and generating a second output signal by variably delaying the first clock signal and an output signal generator for generating a second clock signal, the voltage level of which increases when the first output signal is transitioned from a first logic state to a second logic state and whose voltage level is reduced when the second output signal is transitioned from the second logic state to the first logic state. Accordingly, jitter that exists in the signal output from the delay locked loop circuit is reduced.

43. 发明专利

DE10261571A1 Semiconductor memory device e.g. dynamic RAM, has control circuit that selects the redundant memory line based on the initial comparison of the input address to a first primary stored address when operating in an primary mode 未知
公开(公告)号：DE10261571A1
公开(公告)日：2003-07-17
申请号：DE10261571
申请日：2002-12-23
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： JANG SEONG-JIN , KIM KYU-HYOUN
IPC分类号： G11C29/04 , G11C11/401 , G11C29/00
摘要： A control circuit (100) selects the redundant memory line based on the initial comparison of the input address to a first primary stored address in an primary mode. At an alternate mode, the circuit selects the redundant memory line based on the comparison of the input address to an alternate stored address. The alternate stored address can be stored after the memory device is packaged. Independent claims are also included for the following: (a) a method of repairing a semiconductor memory device; and (b) a post repair method for replacing defective lines with redundancy lines in a memory device

44. 发明专利

DE10128384A1 未知
公开(公告)号：DE10128384A1
公开(公告)日：2002-01-10
申请号：DE10128384
申请日：2001-06-06
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM KYU-HYOUN
IPC分类号： H03L7/093 , H03L7/089 , H01L23/58
摘要： A charge pump circuit capable of preventing coupling and charge injection without increasing a layout area and power consumption is provided. The charge pump circuit includes a pull-up current source, a pull-down current source, a first switching device, and a second switching device. The pull-up current source sources pump-up current to the output node. The pull-down current source includes a current mirror and sinks pump-down current from the output node. In particular, the first switching device is connected between a supply voltage node and the pull-up current source and is switched in response to a pump-up control signal. The second switching device is connected between the second current source and a ground voltage node and is switched in response to a pump-down control signal. The current pump circuit may further include a first dummy capacitor one end of which is connected to a junction between the first switching device and the first current source and a second dummy capacitor one end of which is connected to a junction between the second switching device and the second current source.

45. 发明专利

DE102006051292B4 Takterzeugungsschaltung, Multiphasen-Takterzeuger, Speicherelement, Verfahren zum Erzeugen von Taktsignalen und Verfahren zum Verriegeln der Phase 未知
公开(公告)号：DE102006051292B4
公开(公告)日：2010-08-19
申请号：DE102006051292
申请日：2006-10-24
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM KYU-HYOUN
IPC分类号： H03K3/03 , G11C7/10

46. 发明专利

DE102004036892B4 未知
公开(公告)号：DE102004036892B4
公开(公告)日：2009-10-22
申请号：DE102004036892
申请日：2004-07-20
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： LEE JAE-HYUNG , KIM KYU-HYOUN
IPC分类号： H03K5/02 , H03K19/0185 , H03K3/356 , H03K19/003 , H04L25/02 , H04L25/45

47. 发明专利

DE102006054763A1 未知
公开(公告)号：DE102006054763A1
公开(公告)日：2007-06-28
申请号：DE102006054763
申请日：2006-11-14
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM JIN-YOUNG , KIM KYU-HYOUN
IPC分类号： H03F3/45 , H03L7/081
摘要： A differential amplifier includes an input stage, a biasing unit and a load unit. The input stage receives a first phase signal and at least two phase signals among odd-numbered phase signals, wherein an average of phases of the at least two phase signals has a phase difference of substantially 180 degrees from the first phase signal. The biasing unit is coupled between the input stage and a first power voltage. The load unit is coupled between the input stage and a second power voltage, and configured to output a differential output signal based on differentially amplifying of the first phase signal and the at least two phase signals. Therefore, a duty cycle distortion in an output signal of a duty cycle correction circuit can be prevented.

48. 发明专利

DE102006051292A1 Clock generation circuit for multiphase clock generator, has inverters directly receiving external clock signal and outputting inverted external clock signal, where phase interpolation is performed at each of nodes 未知
公开(公告)号：DE102006051292A1
公开(公告)日：2007-06-06
申请号：DE102006051292
申请日：2006-10-24
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM KYU-HYOUN
IPC分类号： H03K3/03
摘要： The circuit has inverters (INV1-INV4) directly receiving an external clock signal (ECLK) and outputting an inverted external clock signal. Loop circuits (LC1-LCm) are arranged in series with nodes (A1-D1, A2-D2), where each of the loop circuits generates intermediate internal clock signals (CLK1-CLK4). Phase interpolation is performed at each of the nodes, where a phase difference between the adjacent clock signals is 90 degrees. The inverters receive the internal clock signals from a previous loop circuit and output the internal clock signals to a next loop circuit. Independent claims are also included for the following: (1) a multiphase clock generator comprising a clock generation circuit (2) a method of generating internal clock signals (3) a method of locking the phase of a feedback clock signal to an external clock signal.

49. 发明专利

DE102006028966A1 未知
公开(公告)号：DE102006028966A1
公开(公告)日：2007-02-15
申请号：DE102006028966
申请日：2006-06-16
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： PARK MOON-SOOK , KIM KYU-HYOUN
IPC分类号： H03L7/06 , G11C7/22 , G11C11/4063 , H03L7/099

50. 发明专利

DE102005048575A1 Impedance adjustment circuit, e.g. for driver circuit termination, has calibration circuit producing impedance control signal based on voltage that can be generated in response to reference current by emulation of variable impedance circuit 未知
公开(公告)号：DE102005048575A1
公开(公告)日：2006-04-20
申请号：DE102005048575
申请日：2005-10-05
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： CHUNG HOE-JU , LEE JAE-JUN , KIM KYU-HYOUN
IPC分类号： H04L25/02
摘要： The adjustment circuit has a calibration circuit (101) that contains a replica of the variable impedance circuit and that is designed to produce an impedance control signal (FIS1, FIS2) based on a voltage that can be generated in response to a reference current by the emulation of the variable impedance circuit. Preferably the calibration circuit is configured to generate the reference current based on a reference resistor coupled to it, specifically, matching a current in the replica of the variable impedance circuit and a current in the reference resistor. Independent claims are also included for the following: (A) an integrated circuit component (B) an impedance control method for a variable impedance circuit.

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