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41. 发明授权

US06570215B2 Nonvolatile memories with floating gate spacers, and methods of fabrication 有权
公开(公告)号：US06570215B2
公开(公告)日：2003-05-27
申请号：US10199157
申请日：2002-07-18
申请人： Hsing T. Tuan , Vei-Han Chan , Chung Wai Leung , Chia-Shun Hsiao
发明人： Hsing T. Tuan , Vei-Han Chan , Chung Wai Leung , Chia-Shun Hsiao
IPC分类号： H01L2362
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/42328 , H01L29/42336
摘要： In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).

42. 发明授权

US06258668B1 Array architecture and process flow of nonvolatile memory devices for mass storage applications 有权
标题翻译：用于大容量存储应用的非易失性存储器件的阵列架构和处理流程
公开(公告)号：US06258668B1
公开(公告)日：2001-07-10
申请号：US09487501
申请日：2000-01-19
申请人： Peter W. Lee , Hung-Sheng Chen , Vei-Han Chan
发明人： Peter W. Lee , Hung-Sheng Chen , Vei-Han Chan
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0491 , H01L27/115
摘要： In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. the cells are erased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.
摘要翻译：在本发明中，公开了一种用于闪存单元的方法和用于使用闪存单元的架构，以提供具有高存储密度的非易失性存储器。单元格的相邻列共享相同的源，并且连接这些源的源行在存储器布局中垂直运行，连接到相邻列存储单元的源。位线连接到相邻列中的单元格的漏极，并且在每个其他列方案中垂直布置，与源极线交替。由第二层多晶硅制成的字线形成闪存单元的控制栅极，并且在存储器分区的整个宽度上是连续的。使用热电子在垂直页面中进行编程，以将电荷注入到浮动栅极上。通过使用Fowler-Nordheim从浮置栅极到控制栅极的隧道，通过在浮栅的壁上形成的多晶硅氧化物来消除电池。

43. 发明授权

US06188604B1 Flash memory cell & array with improved pre-program and erase characteristics 失效
标题翻译：闪存单元和阵列具有改进的预编程和擦除特性
公开(公告)号：US06188604B1
公开(公告)日：2001-02-13
申请号：US09033106
申请日：1998-03-02
申请人： David K. Y. Liu , Kou-Su Chen , Vei-Han Chan
发明人： David K. Y. Liu , Kou-Su Chen , Vei-Han Chan
IPC分类号： G11C1604
CPC分类号： G11C16/107 , G11C16/16
摘要： A circuit and method for achieving an improved pre-programming of flash memory cells is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for hot electron pre-programming operations. By eliminating the need to pre-program the memory array with hot electrons, the invention provides a signicant improvement for flash arrays, because device life and reliability is extended. In addition, pre-programming time and power is reduced significantly since the operation takes place on a sector (parallel) basis rather than a single bit line (serial) basis, and a charge pump is not needed to generate the current injected into floating gates of cells in the sector.
摘要翻译：公开了一种用于实现闪存单元的改进的预编程的电路和方法。本发明当用于调节闪存单元阵列时，导致这种阵列的耐久性增加，并且消除了对热电子预编程操作的需要。由于不需要用热电子对存储器阵列进行预编程，因此，由于器件寿命和可靠性得到延长，本发明提供了对闪存阵列的显着改进。此外，预编程时间和功率显着降低，因为操作以扇区（并行）为基础而不是基于单个位线（串行）进行，并且不需要电荷泵来产生注入浮动栅极的电流的细胞。

44. 发明授权

US06185133B2 Flash EPROM using junction hot hole injection for erase 失效
标题翻译：闪光EPROM使用结热孔注入进行擦除
公开(公告)号：US06185133B2
公开(公告)日：2001-02-06
申请号：US09105551
申请日：1998-06-26
申请人： Vei-Han Chan , David K. Y. Liu , Kou-Su Chen
发明人： Vei-Han Chan , David K. Y. Liu , Kou-Su Chen
IPC分类号： G11C1604
CPC分类号： G11C16/16
摘要： A novel erase mechanism using junction hot hole injection is disclosed for flash memory cell sector and bulk erase operations. A constant current supply is used so that a suitable junction voltage breakdown can be provided despite expected variations in cell structures, operations, etc. The inventive method eliminates the need for dual polarity voltage supplies for erase operations, and provides a method to achieve a tight distribution of erased cell threshold voltages. In addition, over-erasure problems associated with Fowler-Nordheim tunneling are essentially eliminated.
摘要翻译：公开了一种使用接合热空穴注入的新型擦除机构用于闪存单元扇区和批量擦除操作。使用恒定电流源，以便可以提供适当的结电压击穿，尽管预期的单元结构，操作等的变化。本发明的方法消除了用于擦除操作的双极性电压供应的需要，并且提供了一种实现紧密擦除单元阈值电压的分布。此外，基本上消除了与Fowler-Nordheim隧道相关的过度擦除问题。

45. 发明授权

US5888867A Non-uniform threshold voltage adjustment in flash eproms through gate work function alteration 失效
标题翻译：通过门功功能改变，闪光eprom中的非均匀阈值电压调整
公开(公告)号：US5888867A
公开(公告)日：1999-03-30
申请号：US23241
申请日：1998-02-13
申请人： Janet Wang , Scott D. Luning , Vei-Han Chan , Nicholas H. Tripsas
发明人： Janet Wang , Scott D. Luning , Vei-Han Chan , Nicholas H. Tripsas
IPC分类号： H01L21/28 , H01L21/3215 , H01L21/336 , H01L29/423 , H01L29/49 , H01L21/8247
CPC分类号： H01L29/66825 , H01L21/2807 , H01L21/28105 , H01L21/32155 , H01L29/42324 , H01L29/4966
摘要： Aspects for forming a Flash EPROM cell with an adjustable threshold voltage are described. In a method aspect, the method includes forming a substrate structure to establish a foundation for cell formation, and forming a gate structure with a floating gate layer comprising polysilicon-germanium (poly-SiGe) of a non-uniform Ge concentration on the substrate structure. The method further includes forming source and drain regions within the substrate structure, the drain region having a different threshold voltage than the source region. In a further aspect, a Flash EPROM cell with an adjustable threshold voltage includes a substrate structure as a foundation for the cell. The cell further includes a gate structure on the substrate structure, the gate structure comprising a floating gate layer of polysilicon-germanium (poly-SiGe) of non-uniform Ge concentration. Additionally, source and drain regions are included in the substrate structure bordering the gate structure, the drain region having a differing threshold voltage than the source region.
摘要翻译：描述了形成具有可调阈值电压的闪存EPROM单元的方面。在方法方面，该方法包括形成衬底结构以建立细胞形成的基础，以及在衬底结构上形成具有包含不均匀Ge浓度的多晶锗（多晶硅）的浮栅的栅极结构。该方法还包括在衬底结构内形成源极和漏极区域，漏极区域具有与源极区域不同的阈值电压。在另一方面，具有可调阈值电压的闪存EPROM单元包括作为单元的基础的衬底结构。电池还包括在衬底结构上的栅极结构，栅极结构包括具有不均匀Ge浓度的多晶硅 - 锗（多晶SiGe）的浮栅。此外，源极和漏极区域包括在与栅极结构接壤的衬底结构中，漏极区域具有与源极区域不同的阈值电压。

46. 发明申请

US20090134910A1 RECONFIGURABLE LOGIC STRUCTURES 有权
标题翻译：可重构逻辑结构
公开(公告)号：US20090134910A1
公开(公告)日：2009-05-28
申请号：US12350219
申请日：2009-01-07
申请人： Colin Neal Murphy , Narbeh Derhacobian , Louis Charles Kordus, II , Antonietta Oliva , Vei-Han Chan , Thomas E. Stewart, JR.
发明人： Colin Neal Murphy , Narbeh Derhacobian , Louis Charles Kordus, II , Antonietta Oliva , Vei-Han Chan , Thomas E. Stewart, JR.
IPC分类号： H03K19/177 , G11C11/00
CPC分类号： G11C13/0011 , B82Y10/00 , G11C13/0004 , G11C13/025 , G11C23/00 , H03K19/17736 , H03K19/17748 , H03K19/1778
摘要： Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a switch to produce components such as crossbars, multiplexers, look-up tables (LUTs) and other logic circuits used in programmable logic structures (e.g., (FPGAs)). The programmable, non-volatile memory elements comprise one or more structures based on Phase Change Memory, Programmable Metallization, Carbon Nano-Electromechanical (CNT-NEM), or Metal Nano-Electromechanical device technologies.
摘要翻译：可重构的电子结构和电路使用可编程的非易失性存储元件。可编程的非易失性存储器元件可以执行存储和/或开关的功能，以产生诸如交叉开关，多路复用器，查找表（LUT）和在可编程逻辑结构（例如，（FPGA））中使用的其它逻辑电路的组件，）。可编程的非易失性存储元件包括基于相变存储器，可编程金属化，碳纳米机电（CNT-NEM）或金属纳米机电器件技术的一个或多个结构。

47. 发明授权

US07494849B2 Methods for fabricating multi-terminal phase change devices 有权
标题翻译：制造多端相变装置的方法
公开(公告)号：US07494849B2
公开(公告)日：2009-02-24
申请号：US11267789
申请日：2005-11-03
申请人： Antonietta Oliva , Louis Charles Kordus, II , Narbeh Derharcobian , Vei-Han Chan , Thomas E. Stewart, Jr.
发明人： Antonietta Oliva , Louis Charles Kordus, II , Narbeh Derharcobian , Vei-Han Chan , Thomas E. Stewart, Jr.
IPC分类号： H01L21/06 , H01L45/00
CPC分类号： H01L45/1683 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/1226 , H01L45/126
摘要： Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.
摘要翻译：相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，其中导电性可以根据施加到控制电极的控制信号进行修改。这种结构允许在两个有效端子之间可以产生电连接的应用，连接的控制使用单独的终端或终端实现。因此，可以独立于两个有源端子之间的路径的电阻来增加加热器元件的电阻。这允许使用较小的加热器元件，因此需要较少的电流以在每单位面积上产生相同量的焦耳加热。加热元件的电阻不影响相变装置的总电阻。编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。

48. 发明申请

US20080206922A1 Methods for Fabricating Multi-Terminal Phase Change Devices 有权
标题翻译：多端相变装置的制造方法
公开(公告)号：US20080206922A1
公开(公告)日：2008-08-28
申请号：US12116911
申请日：2008-05-07
申请人： Antonietta Oliva , Louis Charles Kordus , Narbeh Derhacobian , Vei-Han Chan , Thomas E. Stewart
发明人： Antonietta Oliva , Louis Charles Kordus , Narbeh Derhacobian , Vei-Han Chan , Thomas E. Stewart
IPC分类号： H01L45/00
CPC分类号： H01L45/1683 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/1226 , H01L45/126
摘要： Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.
摘要翻译：相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，其导电性可以根据施加到控制电极的控制信号进行修改。这种结构允许在两个有效端子之间可以产生电连接的应用，连接的控制使用单独的终端或终端实现。因此，可以独立于两个有源端子之间的路径的电阻来增加加热器元件的电阻。这允许使用较小的加热器元件，因此需要较少的电流以在每单位面积上产生相同量的焦耳加热。加热元件的电阻不影响相变装置的总电阻。编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。

49. 发明申请

US20070188187A1 Impedance matching and trimming apparatuses and methods using programmable resistance devices 有权
标题翻译：使用可编程电阻器件的阻抗匹配和修整设备和方法
公开(公告)号：US20070188187A1
公开(公告)日：2007-08-16
申请号：US11591734
申请日：2006-11-02
申请人： Antonietta Oliva , Louis Kordus , Vei-Han Chan
发明人： Antonietta Oliva , Louis Kordus , Vei-Han Chan
IPC分类号： H03K17/16
CPC分类号： H04L25/0278 , H03H7/38
摘要： Impedance matching and trimming apparatuses and methods using programmable resistance devices. According to one exemplary embodiment, the impedance matching circuit includes a programmable resistance element, a comparator, a resistor divider having a common node coupled to a first input of the comparator, and an impedance element control circuit coupled between an output of the comparator and the programmable resistance element. The programmable resistance element includes one or more programmable resistance devices (PRDs). Programmed resistances of the programmable resistance element combine with the resistance of an external reference resistor to provide an impedance matched termination. A change in the resistance of the termination impedance causes a change in the output of the comparator. The impedance element control circuit responds to changes in the output of the comparator by providing one or more program control output signals, which control the resistance values of one or more of the PRDs, thereby maintaining an impedance matched termination.
摘要翻译：使用可编程电阻器件的阻抗匹配和修整设备和方法。根据一个示例性实施例，阻抗匹配电路包括可编程电阻元件，比较器，具有耦合到比较器的第一输入的公共节点的电阻器分压器，以及耦合在比较器的输出和可编程电阻元件。可编程电阻元件包括一个或多个可编程电阻器件（PRD）。可编程电阻元件的编程电阻与外部参考电阻的电阻相结合，提供阻抗匹配的端接。端接阻抗的电阻变化导致比较器输出的变化。阻抗元件控制电路通过提供控制一个或多个PRD的电阻值的一个或多个程序控制输出信号来响应比较器的输出的变化，从而保持阻抗匹配的终止。

50. 发明申请

US20070165446A1 SEU hardened latches and memory cells using progrmmable resistance devices 有权
标题翻译： SEU硬化锁存器和存储单元使用可编程电阻器件
公开(公告)号：US20070165446A1
公开(公告)日：2007-07-19
申请号：US11591881
申请日：2006-11-02
申请人： Antonietta Oliva , Vei-Han Chan
发明人： Antonietta Oliva , Vei-Han Chan
IPC分类号： G11C11/00
CPC分类号： G11C11/4125 , B82Y10/00 , G11C5/005 , G11C13/0002 , G11C13/0004 , G11C13/025 , G11C14/009
摘要： Apparatus and methods for reducing single-event upsets (SEUs) in latch-based circuitry (e.g., static random access memory (SRAM) cells) and other digital circuitry. According to an exemplary embodiment, a latch-based circuit includes a radiation-hardened latch having first and second cross-coupled inverters and first and second programmable resistance devices (PRDs). The first PRD is coupled between the output of the first inverter and the input of the second inverter. The second PRD is coupled between the output of the second inverter and the input of the first inverter. The PRDs may be programmed to low or high-resistance states. When SET to a low-resistance state, the latch of the latch-based circuitry may be accessed to read the current logic state stored by the latch or to write a new logic state into the latch. When RESET to a high-resistance state, the latch is in a radiation-hard state, thereby preventing the latch from generating SEUs.
摘要翻译：用于减少基于锁存器的电路（例如，静态随机存取存储器（SRAM）单元）中的单事件故障（SEU）和其它数字电路的装置和方法。根据示例性实施例，基于锁存器的电路包括具有第一和第二交叉耦合的反相器以及第一和第二可编程电阻器件（PRD）的辐射硬化锁存器。第一PRD耦合在第一反相器的输出和第二反相器的输入之间。第二PRD耦合在第二反相器的输出和第一反相器的输入之间。 PRD可以被编程为低电阻或高电阻状态。当SET设置为低电阻状态时，可以访问基于锁存器的电路的锁存器以读取锁存器存储的当前逻辑状态或者将新的逻辑状态写入锁存器。当RESET为高电阻状态时，锁存器处于辐射硬状态，从而防止锁存器产生SEU。

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