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41. 发明申请

US20070230252A1 Row selector for a semiconductor memory device 审中-公开
标题翻译：用于半导体存储器件的行选择器
公开(公告)号：US20070230252A1
公开(公告)日：2007-10-04
申请号：US11726726
申请日：2007-03-21
申请人： Giovanni Campardo , Rino Micheloni
发明人： Giovanni Campardo , Rino Micheloni
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/08 , G11C8/08 , G11C8/10 , G11C8/12
摘要： A row selector for a semiconductor memory including a plurality of memory cells coupled to a corresponding plurality of word lines, the row selector comprising, for each word line: a first biasing circuit path adapted to bias the corresponding word line to a programming voltage when said corresponding word line is selected for selectively performing a program operation on at least one memory cell coupled to the corresponding word line, the first biasing circuit path comprising programming voltage provisioning means adapted to provide the programming voltage; a second biasing circuit path which is adapted to receive, from program-inhibit voltage provisioning means a program inhibit voltage, and to provide to the corresponding word line said program inhibit voltage when the word line is unselected during the program operation, first biasing means for driving the second biasing circuit path in order to control a conduction state thereof; wherein: said first biasing circuit path includes a first transistor controlled to be electrically conductive when the corresponding word line is selected, and to be electrically non-conductive when the corresponding word line is unselected; said first biasing means controls the second biasing circuit path to be conductive when, during the program operation, the corresponding word line is unselected, said second biasing circuit path includes a plurality of series-connected transistors, a number of transistors in said plurality being at least equal to the smallest integer not less than an absolute value of a ratio between a voltage equal to the difference between the programming voltage and the program-inhibit voltage to a predetermined maximum voltage.
摘要翻译：一种用于半导体存储器的行选择器，包括耦合到对应的多个字线的多个存储单元，所述行选择器包括：对于每个字线：第一偏置电路路径，其适于在所述第一偏置电路路径中将相应的字线偏置为编程电压选择对应的字线用于在耦合到对应字线的至少一个存储单元上选择性地执行编程操作，第一偏置电路路径包括适于提供编程电压的编程电压提供装置; 第二偏置电路路径，适于从编程禁止电压供应装置接收编程禁止电压，并且在编程操作期间当字线未被选择时提供给对应的字线，所述编程禁止电压;第一偏置电路驱动第二偏置电路路径以便控制其导通状态; 其中：所述第一偏置电路路径包括当选择相应的字线时被控制为导电的第一晶体管，并且当相应的字线未被选择时为非导通; 当编程操作期间对应的字线未选择时，所述第一偏置装置控制第二偏置电路路径导通，所述第二偏置电路路径包括多个串联连接的晶体管，所述多个晶体管的数量在最小等于不小于等于编程电压和编程禁止电压之间的电压与预定最大电压之间的比的绝对值的绝对值的最小整数。

42. 发明申请

US20070170979A1 Charge pump systems and methods 审中-公开
标题翻译：电荷泵系统和方法
公开(公告)号：US20070170979A1
公开(公告)日：2007-07-26
申请号：US11605193
申请日：2006-11-27
申请人： Giovanni Campardo , Rino Micheloni
发明人： Giovanni Campardo , Rino Micheloni
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A charge pump circuit includes capacitors and a number of forcing circuits for forcing the voltages on various nodes of the charge pump. The forcing circuits ensure that voltage differences across components thereof are up-limited in absolute value by a predetermined maximum voltage equal to a multiple of the absolute value of the difference between developed forcing voltages and lower than an absolute value of a charge pump voltage. The first and second forcing circuits ensure that the voltage differences across components in the forcing circuits are not higher than the predetermined maximum voltage when at least one among the voltages changes to a voltage higher in absolute value than said predetermined maximum voltage.
摘要翻译：电荷泵电路包括电容器和用于强制电荷泵的各种节点上的电压的多个强制电路。强制电路确保其组件之间的电压差绝对值上限在等于显影强制电压之差的绝对值的低于电荷泵电压的绝对值的倍数的预定最大电压。第一和第二强制电路确保当电压中的至少一个变化到绝对值高于所述预定最大电压的电压时，强制电路中的组件之间的电压差不高于预定的最大电压。

43. 发明授权

US06646913B2 Method for storing and reading data in a multilevel nonvolatile memory 有权
公开(公告)号：US06646913B2
公开(公告)日：2003-11-11
申请号：US09976473
申请日：2001-10-11
申请人： Rino Micheloni , Giovanni Campardo
发明人： Rino Micheloni , Giovanni Campardo
IPC分类号： G11C1604
CPC分类号： G11C11/5642 , G11C8/00 , G11C11/56 , G11C11/5621
摘要： The data management method applies to a multilevel nonvolatile memory device having a memory array formed by a plurality of memory cells. Each of the memory cells stores a number of bits that is not an integer power of two, for example three. In this way, one data byte is stored in a non-integer number of memory cells. The managing method includes storing, in a same clock cycle, a data word formed by a plurality of bytes, by programming a preset number of adjacent memory cells. Reading is performed by reading, in a same clock cycle, the stored data word.

44. 发明授权

US06493260B2 Nonvolatile memory device, having parts with different access time, reliability, and capacity 失效
标题翻译：非易失性存储器件，具有不同访问时间，可靠性和容量的部件
公开(公告)号：US06493260B2
公开(公告)日：2002-12-10
申请号：US09957628
申请日：2001-09-19
申请人： Rino Micheloni , Giovanni Campardo
发明人： Rino Micheloni , Giovanni Campardo
IPC分类号： G11C1604
CPC分类号： G11C11/5621 , G11C16/0416 , G11C2211/5641
摘要： The multilevel memory device has a memory section containing cells that can be programmed with a predetermined number of levels greater than two, i.e., a multilevel array, and a memory section containing cells that can be programmed with two levels, i.e., a bilevel array. The multilevel array is used for storing high-density data, for which speed of reading is not essential, for example for storing the operation code of the system including the memory device. On the other hand, the bilevel array is used for storing data for which high speed and reliability of reading is essential, such as the BIOS of personal computers, and the data to be stored in a cache memory. The circuitry parts dedicated to programming, writing of test instructions, and all the functions necessary for the operation of the memory device, can be common to both arrays.
摘要翻译：多电平存储器件具有存储器部分，该存储器部分包含可以以大于2的预定数量的级别（即，多级阵列）编程的单元，以及包含可以用两个级别编程的单元的存储器部分，即双层阵列。多级阵列用于存储高密度数据，读取速度不是必需的，例如用于存储包括存储器件的系统的操作代码。另一方面，双层阵列用于存储读取的高速度和可靠性至关重要的数据，例如个人计算机的BIOS以及要存储在高速缓冲存储器中的数据。专用于编程，写入测试指令的电路部分以及存储器件操作所需的所有功能对于这两个阵列都是共同的。

45. 发明授权

US06456527B1 Nonvolatile multilevel memory and reading method thereof 有权
标题翻译：非易失多级存储器及其读取方法
公开(公告)号：US06456527B1
公开(公告)日：2002-09-24
申请号：US09501131
申请日：2000-02-09
申请人： Giovanni Campardo , Rino Micheloni
发明人： Giovanni Campardo , Rino Micheloni
IPC分类号： G11C1600
CPC分类号： G11C11/5642 , G11C8/14 , G11C11/5621 , G11C16/08
摘要： A multilevel memory stores words formed by a plurality of binary subwords in a plurality of cells, each cell having has a respective threshold value. The cells are arranged on cell rows and columns, are grouped into sectors divided into sector blocks, and are selected via a global row decoder, a global column decoder, and a plurality of local row decoders, which simultaneously supply a ramp voltage to a biasing terminal of the selected cells. Threshold reading comparators are connected to the selected cells, and generate threshold attainment signals when the ramp voltage reaches the threshold value of the selected cells; switches, are arranged between the global word lines and local word lines, opening of the switches is individually controlled by the threshold attainment signals, thereby the local word lines are maintained at a the threshold voltage of the respective selected cell, after opening of the switches.
摘要翻译：多级存储器存储由多个单元格中的多个二进制子词形成的单词，每个单元具有相应的阈值。这些单元被布置在单元行和列上，被分组成扇区区段，并且经由全局行解码器，全局列解码器和多个本地行解码器来选择，其同时向斜率电压提供斜坡电压所选细胞的末端。阈值读取比较器连接到所选择的单元，并且当斜坡电压达到所选择的单元的阈值时产生阈值获取信号; 开关被布置在全局字线和本地字线之间，开关的开启由阈值达到信号单独控制，从而在打开开关之后将局部字线维持在相应选定单元的阈值电压。

46. 发明授权

US06301149B1 Method for reading a multilevel nonvolatile memory and multilevel nonvolatile memory 有权
标题翻译：读取多级非易失性存储器和多级非易失性存储器的方法
公开(公告)号：US06301149B1
公开(公告)日：2001-10-09
申请号：US09513598
申请日：2000-02-25
申请人： Rino Micheloni , Giovanni Campardo
发明人： Rino Micheloni , Giovanni Campardo
IPC分类号： G11C1156
CPC分类号： G11C11/5642
摘要： The sensing circuits comparing the current flowing in the cell with a plurality of reference currents are not identical to each other but differently amplify the compared currents. In particular, the sensing circuit associated with the lowest reference current amplifies the cell current more than the other sensing circuits and to the respective reference current. The current dynamics is thereby increased and it is possible to keep the reading voltage low, since the inherent characteristic of the lowest reference current may be very close to or directly superimposed on that of the immediately preceding memory cell current distribution, retaining the possibility of discriminating between the different logic levels.
摘要翻译：将在单元中流动的电流与多个参考电流进行比较的感测电路彼此不相同，但是不同地放大比较的电流。特别地，与最低参考电流相关联的感测电路比其他感测电路和相应的参考电流更多地放大电池电流。因此，由于最低参考电流的固有特性可能非常接近或直接叠加在紧邻的前一个存储单元电流分布的固有特性上，因此电流动态由此增加，并且可以保持读取电压低，从而保持识别的可能性在不同的逻辑层次之间。

47. 发明授权

US06157225A Driving circuit with three output levels, one output level being a boosted level 有权
标题翻译：驱动电路具有三个输出电平，一个输出电平为提升电平
公开(公告)号：US06157225A
公开(公告)日：2000-12-05
申请号：US234016
申请日：1999-01-19
申请人： Rino Micheloni , Giovanni Campardo , Marco Maccarrone , Maurizio Branchetti
发明人： Rino Micheloni , Giovanni Campardo , Marco Maccarrone , Maurizio Branchetti
IPC分类号： G11C8/08 , H03K19/0185 , H03K17/10
CPC分类号： H03K19/018585 , G11C8/08
摘要： A driving circuit supplied by a supply voltage and a reference voltage, generates an output signal and comprises a first circuit adapted to selectively couple the output signal to the reference voltage or to an internal voltage line internal to the driving circuit in response to a first control signal. The driving circuit also includes a switching circuit adapted to selectively couple the internal voltage line to the supply voltage. A boosting circuit is connected to the internal voltage line and is adapted to bring the internal voltage line to a boosted voltage. The switching circuit and the boosting circuit are controlled by a second control signal to be alternatively activatable, in such a way to bring the internal voltage line either to the supply voltage or to the boosted voltage.
摘要翻译：由电源电压和参考电压提供的驱动电路产生输出信号，并且包括适于选择性地将输出信号耦合到参考电压的第一电路或响应于第一控制的驱动电路内部的内部电压线信号。驱动电路还包括适于选择性地将内部电压线耦合到电源电压的开关电路。升压电路连接到内部电压线，并且适于使内部电压线达到升压电压。开关电路和升压电路由第二控制信号控制，以备可激活的方式，以使内部电压线达到供电电压或升压电压。

48. 发明授权

US6144589A Boosting circuit, particularly for a memory device 有权
标题翻译：升压电路，特别是用于存储器件
公开(公告)号：US6144589A
公开(公告)日：2000-11-07
申请号：US186758
申请日：1998-11-05
申请人： Rino Micheloni , Giovanni Campardo , Donato Ferrario , Carla Maria Golla
发明人： Rino Micheloni , Giovanni Campardo , Donato Ferrario , Carla Maria Golla
IPC分类号： G11C8/08 , G11C8/10 , G11C16/08 , G11C7/00
CPC分类号： G11C16/08 , G11C8/08 , G11C8/10
摘要： A boosting circuit supplied by a first voltage level and a second voltage level, and having an output line capable of taking a third voltage level, the circuit having at least two distinct circuits for generating the third voltage level, the at least two circuits selectively activatable for generating the third voltage level and selectively coupleable to the output line.
摘要翻译：由第一电压电平和第二电压电平提供的升压电路，并具有能够获得第三电压电平的输出线，所述电路具有用于产生第三电压电平的至少两个不同的电路，所述至少两个电路可选择地激活用于产生第三电压电平并选择性地耦合到输出线。

49. 发明授权

US6122200A Row decoder for a flash-EEPROM memory device with the possibility of selective erasing of a sub-group of rows of a sector 有权
标题翻译：用于闪存EEPROM存储器件的行解码器，具有选择性地擦除扇区的一组子组的可能性
公开(公告)号：US6122200A
公开(公告)日：2000-09-19
申请号：US200002
申请日：1998-11-25
申请人： Giovanni Campardo , Rino Micheloni
发明人： Giovanni Campardo , Rino Micheloni
IPC分类号： G11C16/02 , G11C16/08 , G11C16/04
CPC分类号： G11C16/08
摘要： A row decoder includes a plurality of pre-decoding circuits which, starting from row addresses, generate pre-decoding signals and a plurality of final decoding circuits which, starting from the pre-decoding signals, drive the individual rows of the array of the memory device. Each pre-decoding circuit has a push-pull output circuit with a pull-up transistor and a pull-down transistor and four parallel paths for the signal, a first path, supplied with low voltage, which drives the pull-up transistor during reading; a second path, supplied with a positive high voltage, which drives the pull-up transistor during programming and erasing; a third path, supplied with a low voltage, which drives the pull-down transistor during reading and programming; and a fourth path, supplied with a negative high voltage, which drives the pull-down transistor during erasing. Two selection stages enable selectively one of the first and second path, and one of the third and fourth path, depending on the operative step.
摘要翻译：行解码器包括多个预解码电路，其从行地址开始产生预解码信号，并且从预解码信号开始，驱动存储器的阵列的各行，多个最终解码电路设备。每个预译码电路都具有一个具有上拉晶体管和一个下拉晶体管的推挽输出电路，以及四个用于该信号的并行通路，一个提供低电压的第一路径，其在读取期间驱动上拉晶体管 ; 第二路径被提供有正高电压，其在编程和擦除期间驱动上拉晶体管; 提供低电压的第三路径，其在读取和编程期间驱动下拉晶体管; 以及提供有负高电压的第四路径，其在擦除期间驱动下拉晶体管。根据操作步骤，两个选择阶段能够选择性地选择第一和第二路径之一以及第三和第四路径中的一个。

50. 发明授权

US5903498A Low-supply-voltage nonvolatile memory device with voltage boosting 失效
标题翻译：具有升压功能的低电压非易失性存储器件
公开(公告)号：US5903498A
公开(公告)日：1999-05-11
申请号：US877927
申请日：1997-06-18
申请人： Giovanni Campardo , Rino Micheloni , Stefano Commodaro
发明人： Giovanni Campardo , Rino Micheloni , Stefano Commodaro
IPC分类号： G11C16/08 , G11C7/00
CPC分类号： G11C16/08
摘要： The memory device has a plurality of local boost circuits, each connected to a sector of the memory array, and each having a control circuit, at least a respective boost capacitor, and a respective drive circuit. Each drive circuit is only enabled in read mode, on receiving an address-transition-detect signal and a sector enabling signal, for reading memory cells forming part of the respective sector. The boost voltage is only supplied to the final inverter of the row decoder. A clamping diode limits the boost voltage to prevent undesired direct biasing of the PMOS transistors of the final inverters connected to the nonaddressed word lines. And the overvoltage is therefore only supplied locally when and where necessary.
摘要翻译：存储器件具有多个本地升压电路，每个局部升压电路各自连接到存储器阵列的扇区，并且每个具有控制电路，至少相应的升压电容器和相应的驱动电路。每个驱动电路仅在读取模式下被启用，在接收到地址转换检测信号和扇区使能信号时，用于读取形成相应扇区的一部分的存储器单元。升压电压仅提供给行解码器的最终反相器。钳位二极管限制升压电压，以防止连接到非寻址字线的最终逆变器的PMOS晶体管的不期望的直接偏置。因此，过电压仅在必要时在当地提供。

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