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41. 发明授权

US5717242A Integrated circuit having local interconnect for reduing signal cross coupled noise 失效
公开(公告)号：US5717242A
公开(公告)日：1998-02-10
申请号：US633473
申请日：1996-04-17
申请人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L27/11 , H01L29/76 , H01L29/94
CPC分类号： H01L23/5222 , H01L21/76895 , H01L23/5286 , H01L27/11 , H01L2924/0002
摘要： An integrated circuit is provided having an improved interconnect structure. The interconnect structure includes a power-coupled local interconnect which is always retained at VDD or VSS (i.e., ground) level. The local interconnect resides a dielectric-spaced distance below critical runs of overlying interconnect. The powered local interconnect serves to sink noise transients from the critical conductors to ensure that circuits connected to the conductors do not inoperably function. Accordingly, the local interconnect extends along a substantial portion of the conductor length, and is either wider or narrower than the conductor under which it extends. The local interconnect can either be polysilicon, doped polysilicon, polycide, refractory metal silicide, or multi-level refractory metal.

42. 发明授权

US06326298B1 Substantially planar semiconductor topography using dielectrics and chemical mechanical polish 有权
标题翻译：使用电介质和化学机械抛光的基本平面的半导体形貌
公开(公告)号：US06326298B1
公开(公告)日：2001-12-04
申请号：US09513293
申请日：2000-02-25
申请人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L214763
CPC分类号： H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a multilevel interconnect structure having a globally planarized upper surface. Dielectrics are deposited upon a semiconductor to minimize pre-existing disparities in topographical height and to create an upper surface topography having a polish rate greater than that of lower regions. Subsequent chemical mechanical polishing produces a substantially planar surface.
摘要翻译：一种用于形成具有全局平坦化的上表面的多层互连结构的方法。电介质沉积在半导体上以最小化形貌高度上的先前存在的差异并产生具有比下部区域更高的抛光速率的上表面形貌。随后的化学机械抛光产生基本平坦的表面。

43. 发明授权

US6153833A Integrated circuit having interconnect lines separated by a dielectric having a capping layer 有权
标题翻译：具有由具有封盖层的电介质隔开的互连线的集成电路
公开(公告)号：US6153833A
公开(公告)日：2000-11-28
申请号：US148098
申请日：1998-09-04
申请人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/312 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/04 , H05K1/03
CPC分类号： H01L23/5222 , H01L23/5226 , H01L23/5283 , H01L2924/0002
摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. Accordingly, a space between conductors on one level is directly above or directly below a conductor within another level. The staggered interconnect lines are advantageously used in densely spaced regions to reduce the interlevel and intralevel capacitance. Furthermore, an interlevel and an intralevel dielectric structure includes optimally placed low K dielectrics which exist in critical spaced areas to minimize capacitive coupling and propagation delay problems. The low K dielectric, according to one embodiment, includes a capping dielectric which is used to prevent corrosion on adjacent metallic conductors, and serves as an etch stop when conductors are patterned. The capping dielectric further minimizes the overall intrinsic stress of the resulting intralevel and interlevel dielectric structure.
摘要翻译：提供了一种改进的多级互连结构。互连结构包括多个级别的导体，其中一个层上的导体相对于另一层上的导体交错。因此，在一个级别上的导体之间的空间位于另一层内的导体的正上方或正下方。交错的互连线有利地用于密集间隔的区域以减少层间和层间电容。此外，层间和层间介质结构包括存在于临界间隔区域中的最佳放置的低K电介质，以最小化电容耦合和传播延迟问题。根据一个实施例的低K电介质包括封盖电介质，其用于防止相邻金属导体上的腐蚀，并且当导体被图案化时用作蚀刻停止层。封盖电介质进一步最小化所得到的层间和层间电介质结构的整体固有应力。

44. 发明授权

US6150721A Integrated circuit which uses a damascene process for producing staggered interconnect lines 有权
标题翻译：集成电路，其使用镶嵌工艺来产生交错的互连线
公开(公告)号：US6150721A
公开(公告)日：2000-11-21
申请号：US132454
申请日：1998-08-11
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/768 , H01L23/522 , H01L23/48
CPC分类号： H01L21/76807 , H01L21/768 , H01L23/5222 , H01L2924/0002
摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.
摘要翻译：提供了一种改进的多级互连结构。互连结构包括多个级别的导体，其中一个层上的导体相对于另一层上的导体交错。在密集间隔的互连区域中，插入的导体被拉至不同的高度级以减小互连之间的电容耦合。通过交错密集图案化区域中的每隔一个互连线，互连能够承载更大量的电流并且在其间具有最小的电容耦合。

45. 发明授权

US6137182A Method of reducing via and contact dimensions beyond photolithography equipment limits 有权
标题翻译：降低光刻设备限制以外的通孔和接触尺寸的方法
公开(公告)号：US6137182A
公开(公告)日：2000-10-24
申请号：US137471
申请日：1998-08-20
申请人： Fred N. Hause , Mark I. Gardner , Robert Dawson
发明人： Fred N. Hause , Mark I. Gardner , Robert Dawson
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76816
摘要： A semiconductor process for forming an interlevel contact. A semiconductor wafer is provided with a semiconductor substrate, a first conductive layer formed on the substrate, and a dielectric layer formed on the conductive layer. A border layer, preferably comprised of polysilicon or silicon nitride is formed on the dielectric layer. Portions of the border layer are then selectively removed to expose an upper surface of a spacer region of the dielectric layer, the selective removal of the border layer resulting in a border layer having an annular sidewall extending upward from the dielectric layer and encircling the spacer region. A spacer structure is then formed on the annular sidewall, preferably, the spacer structure is formed by chemically vapor depositing a spacer material and anisotropically etching the spacer material to just clear in the planar regions with minimum overetch. The spacer structure thereby covering peripheral portions of the spacer region such that an upper surface of a contact region remains exposed. Portions of the dielectric layer within the contact region are then removed to form a via extending from an upper surface of the spacer structure to an upper surface of the first conductive layer. Preferably, the lateral dimension of the spacer region is approximately equal to the minimum feature size of a photolithography exposure apparatus in the lateral dimension of the via at substantially less than the minimum feature size of the photolithography exposure apparatus.
摘要翻译：一种用于形成层间接触的半导体工艺。半导体晶片设置有半导体衬底，形成在衬底上的第一导电层和形成在导电层上的电介质层。在电介质层上形成优选由多晶硅或氮化硅构成的边界层。然后选择性地去除边界层的部分以暴露电介质层的间隔区域的上表面，选择性地去除边界层，导致边界层具有从电介质层向上延伸并环绕间隔区域的环形侧壁。然后在环形侧壁上形成间隔结构，优选地，间隔物结构通过化学气相沉积间隔物材料形成，并且各向异性地蚀刻间隔物材料，以便在具有最小过氧化物的平面区域中刚好清除。间隔结构由此覆盖间隔区域的周边部分，使得接触区域的上表面保持暴露。然后去除接触区域内的电介质层的部分以形成从间隔物结构的上表面延伸到第一导电层的上表面的通孔。优选地，间隔区域的横向尺寸基本上等于光刻曝光装置在通孔的横向尺寸中的最小特征尺寸，其基本上小于光刻曝光装置的最小特征尺寸。

46. 发明授权

US6091149A Dissolvable dielectric method and structure 有权
标题翻译：溶解介电法和结构
公开(公告)号：US6091149A
公开(公告)日：2000-07-18
申请号：US251059
申请日：1999-02-18
申请人： Fred N. Hause , Basab Bandyopadhyay , Robert Dawson , H. Jim Fulford, Jr. , Mark W. Michael , William S. Brennan
发明人： Fred N. Hause , Basab Bandyopadhyay , Robert Dawson , H. Jim Fulford, Jr. , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/768 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/7682
摘要： A fabrication process is provided that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of air. In one embodiment of the invention, a first interconnect level is formed on a barrier layer. A temporary support material is then formed over the first interconnect level and a second level of interconnect is formed on the temporary support material. Prior to formation of the second interconnect level, a plurality of pillar openings are formed in the temporary material and filled with a conductive material. In addition to providing a contact between the first and second level of interconnects, the pillars provide mechanical support for the second interconnect level. The temporary material is dissolved in a solution that attacks the temporary material but leaves the interconnect material and pillar material intact. In one embodiment of the invention, a passivation layer is formed on the second interconnect level prior to dissolving the temporary material. The air gap dielectric can be used with more than two levels of interconnect, if desired.
摘要翻译：提供一种制造工艺，其产生气隙电介质，其中在临时支撑材料上形成多层互连结构。随后将临时材料溶解掉，留下由空气组成的层间和层间电介质。在本发明的一个实施例中，在阻挡层上形成第一互连电平。然后在第一互连层上形成临时支撑材料，并在临时支撑材料上形成第二层互连。在形成第二互连级别之前，在临时材料中形成多个柱状开口并填充有导电材料。除了在第一和第二级互连之间提供接触之外，支柱为第二互连电平提供机械支撑。临时材料溶解在攻击临时材料的溶液中，但使互连材料和支柱材料完好无损。在本发明的一个实施例中，在溶解临时材料之前，在第二互连层上形成钝化层。如果需要，气隙电介质可以与多于两个级别的互连一起使用。

47. 发明授权

US6049134A Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization 失效
标题翻译：用于制造具有最佳金属互连布局以实现全局平坦化的集成电路的掩模生成技术
公开(公告)号：US6049134A
公开(公告)日：2000-04-11
申请号：US15821
申请日：1998-01-29
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/033 , H01L21/3105 , H01L21/768 , H01L29/72 , H01L21/283
CPC分类号： H01L21/0334 , H01L21/31051 , H01L21/76819
摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.
摘要翻译：提供了一种光刻掩模衍生方法，用于改善沉积在由衍生的光刻掩模形成的导体上的层间电介质的整体平面性。衍生出光刻掩模，使得非操作导体彼此间隔开最小距离和与操作导体间隔开的规则间隔排列的导体，其上可使用例如化学机械的电介质层沉积并容易地平坦化抛光技术。所得的层间电介质上表面在整个半导体形貌上被全局平坦化到均匀的高度。操作导体与非操作导体不相似，因为操作导体连接在可操作的集成电路的电路中。非操作导体不在集成电路路径内连接，并且通常浮动或连接到电源。因此，非操作导体对集成电路功能没有贡献，而不是为覆盖的层间电介质提供结构平面性。掩模推导方法适用于金属互连光刻掩模或多晶硅互连光刻掩模。

48. 发明授权

US5998293A Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect 失效
标题翻译：具有气隙的集成电路的多层互连结构和分离互连级别的柱
公开(公告)号：US5998293A
公开(公告)日：1999-12-07
申请号：US67425
申请日：1998-04-28
申请人： Robert Dawson , Mark W. Michael , William S. Brennan , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause
发明人： Robert Dawson , Mark W. Michael , William S. Brennan , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause
IPC分类号： H01L21/768 , H01L23/522 , H01L21/283
CPC分类号： H01L23/5226 , H01L21/7682 , H01L21/76885 , H01L23/5222 , H01L2924/0002
摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes pillars spaced from each other across a wafer. The pillars are placed between levels of interconnect or between an interconnect level and a semiconductor substrate. The pillars are spaced from each other by an air gap, such that each conductor within a level of interconnect is spaced by air from one another. Furthermore, each conductor within one level of interconnect is spaced by air from each conductor within another level of interconnect. Air gaps afford a smaller interlevel and intralevel capacitance within the multilevel interconnect structure, and a smaller parasitic capacitance value affords minimal propagation delay and cross-coupling noise of signals sent through the conductors. The air gaps are formed by dissolving a sacrificial dielectric, and the conductors are prevented from bending or warping in regions removed of sacrificial dielectric by employing anodization on not just the upper surfaces of each conductor, but the sidewalls as well. The upper and sidewall anodization provides a more rigid metal conductor structure than if merely the upper or sidewall surfaces were anodized. Accordingly, the pillars can be spaced further apart and yet provide all necessary support to the overlying conductors.
摘要翻译：提供了一种改进的多级互连结构。互连结构包括跨越晶片彼此间隔开的柱。支柱放置在互连层之间或互连层和半导体衬底之间。支柱通过空气间隙彼此分开，使得互连级别内的每个导体彼此间隔着空气。此外，一个级别的互连中的每个导体在另一个互连级别内的每个导体间隔着空气。空气间隙在多电平互连结构内提供较小的层间和体积电容，并且较小的寄生电容值提供通过导体发送的信号的最小传播延迟和交叉耦合噪声。通过溶解牺牲电介质形成气隙，并且通过不仅在每个导体的上表面，而且侧壁上采用阳极氧化，防止导体在去除牺牲电介质的区域中弯曲或翘曲。上侧壁和侧壁阳极氧化提供了比仅仅将上表面或侧壁表面阳极氧化的更刚性的金属导体结构。因此，支柱可以进一步间隔开，并且向上覆的导体提供所有必要的支撑。

49. 发明授权

US5963783A In-line detection and assessment of net charge in PECVD silicon dioxide (oxide) layers 失效
标题翻译：在线检测和评估PECVD二氧化硅（氧化物）层中的净电荷
公开(公告)号：US5963783A
公开(公告)日：1999-10-05
申请号：US93239
申请日：1998-06-08
申请人： John K. Lowell , Fred N. Hause , Robert Dawson
发明人： John K. Lowell , Fred N. Hause , Robert Dawson
IPC分类号： H01L21/316 , H01L21/66 , G01R31/265
CPC分类号： H01L21/31612 , H01L21/02112 , H01L21/02274 , H01L22/14
摘要： The present method provides for the detection and assessment of the net charge in a PECVD oxide layer deposited on a surface of a semiconductor substrate. Electrical potential differences across PECVD oxide layers on as-produced semiconductor substrates are measured. Resultant PECVD oxide charge derivative values are plotted on an control chart and compared to calculated control parameters. All measurement techniques are non-contact and non-destructive, allowing them to be performed on as-processed semiconductor substrates at any time during or following a wafer fabrication process. In a first embodiment, a contact potential difference V.sub.CPD between a vibrating electrode and the semiconductor substrate is measured while the semiconductor substrate beneath the vibrating electrode is subjected to a constant beam of high intensity illumination. The resultant value of V.sub.CPD is equal to the electrical potential difference across the PECVD oxide layer V.sub.OX (plus a constant). In a second embodiment, the semiconductor substrate is not illuminated curing the measurement of V.sub.CPD. A conventional SPV apparatus is used to measure the surface barrier potential V.sub.SP of the semiconductor substrate. Subtracting the measured value of V.sub.SP from the measured value of V.sub.CPD yields the value of V.sub.OX (plus a constant).
摘要翻译：本方法提供了在沉积在半导体衬底的表面上的PECVD氧化物层中的净电荷的检测和评估。测量生成半导体衬底上的PECVD氧化物层的电位差。将得到的PECVD氧化物电荷衍生值绘制在控制图上并与计算的控制参数进行比较。所有测量技术都是非接触式和非破坏性的，允许它们在晶片制造过程中或之后的任何时间在经处理的半导体衬底上进行。在第一实施例中，测量振动电极和半导体衬底之间的接触电位差VCPD，同时振动电极下方的半导体衬底经受恒定的高强度照明光束。 VCPD的结果值等于PECVD氧化物层VOX（加常数）之间的电位差。在第二实施例中，半导体衬底不被照射固化VCPD的测量。常规的SPV装置用于测量半导体衬底的表面势垒电位VSP。从VCPD的测量值中减去VSP的测量值，得到VOX的值（加一个常数）。

50. 发明授权

US5926717A Method of making an integrated circuit with oxidizable trench liner 失效
标题翻译：制造具有可氧化沟槽衬垫的集成电路的方法
公开(公告)号：US5926717A
公开(公告)日：1999-07-20
申请号：US763313
申请日：1996-12-10
申请人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L21/762 , H01L21/76 , H01L21/62
CPC分类号： H01L21/76227
摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a trench in the semiconductor substrate between said first active region and said second active region. A first dielectric layer is then formed on said trench and a polysilicon layer is deposited on said first dielectric layer. The polysilicon layer is then thermally oxidized to form a second dielectric layer. Preferably the first dielectric is a thermal oxide 40 to 500 angstroms in thickness consuming less than 200 angstroms of said first active region and said second active region. The polysilicon layer is preferably between 1000 to 2000 angstroms.
摘要翻译：一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。该方法包括在所述第一有源区和所述第二有源区之间的半导体衬底中形成沟槽。然后在所述沟槽上形成第一电介质层，并且在所述第一电介质层上沉积多晶硅层。然后将多晶硅层热氧化以形成第二介电层。优选地，第一电介质是厚度为40-500埃的热氧化物，其消耗小于200埃的所述第一有源区和所述第二活性区。多晶硅层优选为1000〜2000埃。

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