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41. 发明申请

US20120246407A1 METHOD AND SYSTEM TO IMPROVE UNALIGNED CACHE MEMORY ACCESSES 审中-公开
标题翻译：改进高速缓存存储器访问的方法和系统
公开(公告)号：US20120246407A1
公开(公告)日：2012-09-27
申请号：US13052468
申请日：2011-03-21
申请人： WILLIAM C. HASENPLAUGH , Tryggve Fossum
发明人： WILLIAM C. HASENPLAUGH , Tryggve Fossum
IPC分类号： G06F12/08
CPC分类号： G06F12/0846
摘要： A method and system to improve unaligned cache memory accesses. In one embodiment of the invention, a processing unit has logic to facilitate access of at least two cache memory lines of a cache memory in a single read operation. By doing so, it avoids additional read operations or cycles to read the required data that is cached in more than one cache memory line. Embodiments of the invention facilitate the streaming of unaligned vector loads that does not require substantially more power than streaming aligned vector loads. For example, in one embodiment of the invention, the streaming of unaligned vector loads consumes less than two times the power requirements of streaming aligned vector loads.
摘要翻译：一种改善未对齐缓存存储器访问的方法和系统。在本发明的一个实施例中，处理单元具有便于在单次读取操作中访问高速缓冲存储器的至少两个高速缓存存储器线路的逻辑。通过这样做，它避免了额外的读取操作或循环来读取缓存在多个缓存存储器行中的所需数据。本发明的实施例有助于不需要比流对齐矢量负载大得多的功率的未对齐矢量负载的流。例如，在本发明的一个实施例中，未对齐矢量负载的流量消耗小于流对齐矢量负载的功率需求的两倍。

42. 发明授权

US07389440B2 Method, system, and apparatus for improving multi-core processor performance 有权
标题翻译：用于提高多核处理器性能的方法，系统和设备
公开(公告)号：US07389440B2
公开(公告)日：2008-06-17
申请号：US11336681
申请日：2006-01-20
申请人： Daniel W. Bailey , Todd Dutton , Tryggve Fossum
发明人： Daniel W. Bailey , Todd Dutton , Tryggve Fossum
IPC分类号： G06F1/00 , G06F1/26
CPC分类号： G06F1/324 , G06F1/3228 , G06F1/3287 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D10/24
摘要： A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.
摘要翻译：用于核心配给逻辑以使多核处理器的核能够遵守各种功率和热限制的系统，装置和方法。

43. 发明申请

US20060117199A1 Method, system, and apparatus for improving multi-core processor performance 有权
公开(公告)号：US20060117199A1
公开(公告)日：2006-06-01
申请号：US11336015
申请日：2006-01-20
申请人： Daniel Bailey , Todd Dutton , Tryggve Fossum
发明人： Daniel Bailey , Todd Dutton , Tryggve Fossum
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3228 , G06F1/3287 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D10/24
摘要： A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.

44. 发明申请

US20060075301A1 Converting merge buffer system-kill errors to process-kill errors 有权
标题翻译：将合并缓冲区系统杀死错误转换为进程杀死错误
公开(公告)号：US20060075301A1
公开(公告)日：2006-04-06
申请号：US10948904
申请日：2004-09-24
申请人： Tryggve Fossum , Yaron Shragai , Ugonna Echeruo , Shubhendu Mukherjee
发明人： Tryggve Fossum , Yaron Shragai , Ugonna Echeruo , Shubhendu Mukherjee
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F9/3824 , G06F9/3861 , G06F11/0715 , G06F11/1016 , G06F11/1032
摘要： An apparatus includes a buffer that collects store instruction information associated with one or more processes. The collected store instruction information includes data and addresses where the data are to be stored. The apparatus also includes a buffer control that drains the buffer of store instructions associated with a first process before it collects store instructions associated with a second process.
摘要翻译：一种装置包括收集与一个或多个处理相关联的存储指令信息的缓冲器。收集的存储指令信息包括要存储数据的数据和地址。该装置还包括缓冲器控制，其在收集与第二进程相关联的存储指令之前，将与第一进程相关联的存储指令的缓冲器排出。

45. 发明授权

US5148528A Method and apparatus for simultaneously decoding three operands in a variable length instruction when one of the operands is also of variable length 失效
标题翻译：同时在可变长度指令中同时解码三个操作的方法和装置，其中一个操作也是可变长度
公开(公告)号：US5148528A
公开(公告)日：1992-09-15
申请号：US307347
申请日：1989-02-03
申请人： David B. Fite , John E. Murray , Tryggve Fossum
发明人： David B. Fite , John E. Murray , Tryggve Fossum
IPC分类号： G06F9/32 , G06F9/30 , G06F9/318 , G06F9/34 , G06F9/38
CPC分类号： G06F9/30192 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/34 , G06F9/3816 , G06F9/3822 , G06F9/3838
摘要： An instruction decoder for a pipelined data processing unit simultaneously decodes two source specifiers and one destination specifier. All three of the specifiers can be register specifiers in which the specified operand is the content of a specified register. Any one of the specifiers can be a complex specifier designating an index register, a base register, and a displacement. Any one of the source specifiers can specify short literal data. Data for locating the two source operands and the destination operand are transmitted over parallel buses to an execution unit, so that most instructions are executed at a rate of one instruction per clock cycle. The complex specifier can have a variable length determined by its data type as well as its addressing mode. In particular, the complex specifier may specify a long length of extended immediate data that is received through the instruction buffer over a number of clock cycles.

46. 发明申请

US20140189413A1 DISTRIBUTED POWER MANAGEMENT FOR MULTI-CORE PROCESSORS 有权
标题翻译：多核处理器的分布式电源管理
公开(公告)号：US20140189413A1
公开(公告)日：2014-07-03
申请号：US13732289
申请日：2012-12-31
申请人： William C. Hasenplaugh , Tryggve Fossum
发明人： William C. Hasenplaugh , Tryggve Fossum
IPC分类号： G06F1/28
CPC分类号： G06F1/3206 , G06F1/3203 , G06F1/3234 , G06F1/324 , G06F1/3243 , G06F1/3275 , G06F1/3287 , G06F1/3296 , G06F9/3885 , G06F9/5094 , Y02D10/152 , Y02D10/22
摘要： A system and method for performing distributed power control in a processor comprising an array of cores enables each core to regulate power at least partially independently. Global power management settings are made accessible to all cores and communication between cores propagates power consumption information between nearest neighbors in the array. Each core attempts to best regulate its own power consumption in accordance with global power consumption information and/or specific instructions from a global power manager. In this manner local opportunistic load balancing may be achieved in a scalable manner suitable for a large array of cores.
摘要翻译：用于在包括核心阵列的处理器中执行分布式功率控制的系统和方法使得每个核心能够至少部分地独立地调节功率。所有核心都可以访问全局电源管理设置，并且内核之间的通信会传播阵列中最近邻居之间的功耗信息。每个核心都尝试根据全球功耗信息和/或来自全球电源管理员的特定指令来最佳地调节其自身的功耗。以这种方式，可以以适合于大型核心阵列的可扩展方式来实现本地机会性负载平衡。

47. 发明授权

US08769201B2 Technique for controlling computing resources 有权
标题翻译：控制计算资源的技术
公开(公告)号：US08769201B2
公开(公告)日：2014-07-01
申请号：US12315331
申请日：2008-12-02
申请人： William Hasenplaugh , Joel Emer , Tryggve Fossum , Aamer Jaleel , Simon Steely
发明人： William Hasenplaugh , Joel Emer , Tryggve Fossum , Aamer Jaleel , Simon Steely
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/08
CPC分类号： G06F12/0802 , G06F9/5016 , G06F12/0862 , G06F12/0866 , G06F2209/501 , Y02D10/22
摘要： A technique to enable resource allocation optimization within a computer system. In one embodiment, a gradient partition algorithm (GPA) module is used to continually measure performance and adjust allocation to shared resources among a plurality of data classes in order to achieve optimal performance.
摘要翻译：一种在计算机系统内实现资源分配优化的技术。在一个实施例中，使用梯度分割算法（GPA）模块来连续地测量性能并且调整对多个数据类之间的共享资源的分配，以便实现最佳性能。

48. 发明授权

US07788519B2 Method, system, and apparatus for improving multi-core processor performance 有权
标题翻译：用于提高多核处理器性能的方法，系统和设备
公开(公告)号：US07788519B2
公开(公告)日：2010-08-31
申请号：US11686861
申请日：2007-03-15
申请人： Daniel W. Bailey , Todd Dutton , Tryggve Fossum
发明人： Daniel W. Bailey , Todd Dutton , Tryggve Fossum
IPC分类号： G06F1/00 , G06F1/26 , G06F12/00 , G06F15/00
CPC分类号： G06F1/324 , G06F1/3228 , G06F1/3287 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D10/24
摘要： A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.
摘要翻译：用于核心配给逻辑以使多核处理器的核能够遵守各种功率和热约束的系统，装置和方法。

49. 发明授权

US07392414B2 Method, system, and apparatus for improving multi-core processor performance 有权
公开(公告)号：US07392414B2
公开(公告)日：2008-06-24
申请号：US11336015
申请日：2006-01-20
申请人： Daniel W. Bailey , Todd Dutton , Tryggve Fossum
发明人： Daniel W. Bailey , Todd Dutton , Tryggve Fossum
IPC分类号： G06F1/00 , G06F1/26
CPC分类号： G06F1/324 , G06F1/3228 , G06F1/3287 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D10/24
摘要： A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.

50. 发明申请

US20070300016A1 Shared cache performance 有权
标题翻译：共享缓存性能
公开(公告)号：US20070300016A1
公开(公告)日：2007-12-27
申请号：US11472877
申请日：2006-06-21
申请人： Tryggve Fossum
发明人： Tryggve Fossum
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F12/084
摘要： A method and apparatus for improving shared cache performance. In one embodiment, the present invention includes a cache having multiple ways. A locality tester measures a first locality of a first process and second locality of a second process. A first set of multiple ways stores the data used by the first process and a second set of multiple ways stores the data used by the second process, where the second set is a superset of the first set.
摘要翻译：一种用于提高共享缓存性能的方法和装置。在一个实施例中，本发明包括具有多种方式的高速缓存。地点测试者测量第一进程的第一地点和第二进程的第二地点。第一组多路存储第一过程使用的数据，第二组多路存储由第二过程使用的数据，其中第二集合是第一集合的超集。

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