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41. 发明申请

US20080237718A1 METHODS OF FORMING HIGHLY ORIENTED DIAMOND FILMS AND STRUCTURES FORMED THEREBY 审中-公开
标题翻译：形成高精度金刚石薄膜的方法及其形成的结构
公开(公告)号：US20080237718A1
公开(公告)日：2008-10-02
申请号：US11694626
申请日：2007-03-30
申请人： Vladimir Noveski , Sujit Sharan , Aleksandar Aleksov
发明人： Vladimir Noveski , Sujit Sharan , Aleksandar Aleksov
IPC分类号： H01L27/12 , H01L21/8238
CPC分类号： H01L27/0688 , H01L21/8221 , H01L21/84
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a first HOD layer on a first side of a first silicon substrate, forming a CMOS region on a second side of the silicon substrate, forming amorphous silicon on the CMOS region, recrystallizing the amorphous silicon to form a first single crystal silicon layer, and forming a second HOD layer on the first single crystal silicon layer.
摘要翻译：描述形成微电子器件的方法和相关结构。这些方法可以包括在第一硅衬底的第一侧上形成第一HOD层，在硅衬底的第二侧上形成CMOS区域，在CMOS区域上形成非晶硅，使非晶硅重结晶以形成第一单晶硅层，并在第一单晶硅层上形成第二HOD层。

42. 发明授权

US07151054B2 Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks 有权
标题翻译：形成和利用抗反射材料层的半导体加工方法，以及形成晶体管栅叠层的方法
公开(公告)号：US07151054B2
公开(公告)日：2006-12-19
申请号：US10805557
申请日：2004-03-19
申请人： Gurtej S. Sandhu , Sujit Sharan
发明人： Gurtej S. Sandhu , Sujit Sharan
IPC分类号： H01L21/4763
CPC分类号： G03F7/091 , H01L21/0214 , H01L21/02211 , H01L21/02274 , H01L21/0276 , H01L21/28123 , H01L21/3145
摘要： In one aspect, the invention includes a semiconductor processing method comprising exposing silicon, nitrogen and oxygen in gaseous form to a high density plasma during deposition of a silicon, nitrogen and oxygen containing solid layer over a substrate.In another aspect, the invention includes a gate stack forming method, comprising: a) forming a polysilicon layer over a substrate; b) forming a metal silicide layer over the polysilicon layer; c) depositing an antireflective material layer over the metal silicide utilizing a high density plasma; d) forming a layer of photoresist over the antireflective material layer; e) photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist; and f) transferring a pattern from the patterned masking layer to the antireflective material layer, metal silicide layer and is polysilicon layer to pattern the antireflective material layer, metal silicide layer and polysilicon layer into a gate stack.
摘要翻译：在一个方面，本发明包括一种半导体处理方法，包括在衬底上沉积含硅，含氮和氧的固体层时，将硅，氮和氧气体暴露于高密度等离子体。在另一方面，本发明包括一种栅堆叠形成方法，包括：a）在衬底上形成多晶硅层; b）在所述多晶硅层上形成金属硅化物层; c）利用高密度等离子体在金属硅化物上沉积防反射材料层; d）在抗反射材料层上形成一层光致抗蚀剂; e）光刻地图案化所述光致抗蚀剂层以从所述光致抗蚀剂层形成图案化掩模层; 以及f）将图案从图案化掩模层转移到抗反射材料层，金属硅化物层，并且是将抗反射材料层，金属硅化物层和多晶硅层图案化成栅叠层的多晶硅层。

43. 发明申请

US20060202283A1 Metal silicide adhesion layer for contact structures 审中-公开
标题翻译：用于接触结构的金属硅化物粘合层
公开(公告)号：US20060202283A1
公开(公告)日：2006-09-14
申请号：US11418159
申请日：2006-05-03
申请人： Ammar Deraa , Sujit Sharan , Paul Castrovillo
发明人： Ammar Deraa , Sujit Sharan , Paul Castrovillo
IPC分类号： H01L29/76
CPC分类号： H01L21/76846 , H01L21/28518 , H01L21/28556 , H01L21/76855 , H01L21/76877 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A high aspect ratio contact structure using a metal silicide adhesion layer that is interposed between titanium and titanium nitride (TiN) to promote adhesion of TiN to Ti. The metal silicide adhesion layer created from silicon doped CVD Ti can be deposited over the unreacted Ti after the silicidation reaction or deposited directly on the silicon substrate in place of CVD Ti. The contact structure further includes contact fill that is comprised of TiCl4 based TiN, which affords improved step coverage in the contact structure.
摘要翻译：使用介于钛和氮化钛（TiN）之间的金属硅化物粘附层的高纵横比接触结构以促进TiN与Ti的粘附。由硅掺杂的CVD Ti产生的金属硅化物粘附层可以在硅化反应之后沉积在未反应的Ti上，或者直接沉积在硅衬底上而不是CVD Ti。接触结构还包括由基于TiCl 4的TiN组成的接触填充，其提供接触结构中改进的台阶覆盖。

44. 发明授权

US07093559B2 Method for PECVD deposition of selected material films 有权
标题翻译： PECVD沉积所选材料膜的方法
公开(公告)号：US07093559B2
公开(公告)日：2006-08-22
申请号：US09825611
申请日：2001-04-03
申请人： Sujit Sharan , Gurtej S. Sandhu
发明人： Sujit Sharan , Gurtej S. Sandhu
IPC分类号： C23C16/44
CPC分类号： C23C16/14 , C23C16/08 , C23C16/34 , H01J37/32321 , H01L21/28556 , H01L21/28568 , H01L2224/48091 , H01L2224/48247 , H01L2224/48471 , H01L2924/00014 , H01L2924/01012 , H01L2924/01019 , H01L2924/01029 , H01L2924/04941 , H01L2924/19041 , H01L2924/00 , H01L2224/48227 , H01L2224/4554
摘要： A process for PECVD of selected material films on a substrate comprising the steps of placing a substrate in a PECVD chamber and maintaining the chamber under vacuum pressure while introducing a precursor gas, a reactant gas, and an ionization enhancer agent into the chamber. A plasma is generated from the gases within the chamber. The energy generating the plasma causes the formation of charged species. The resulting charged species of the ionization enhancer agent assists in the formation of chemically reactive species of at least the precursor.
摘要翻译：一种用于衬底上所选材料膜的PECVD的方法，包括以下步骤：将衬底放置在PECVD腔室中，并将腔室保持在真空压力下，同时将前体气体，反应气体和电离增强剂引入腔室。从室内的气体产生等离子体。产生等离子体的能量导致带电物质的形成。所得到的电离增强剂的带电物质有助于形成至少前体的化学反应性物质。

45. 发明授权

US06974726B2 Silicon wafer with soluble protective coating 失效
标题翻译：具有可溶性保护涂层的硅片
公开(公告)号：US06974726B2
公开(公告)日：2005-12-13
申请号：US10748446
申请日：2003-12-30
申请人： Ashay A. Dani , Gudbjorg H. Oskarsdottir , Chris Matayabas, Jr. , Sujit Sharan , Chris L. Rumer , Beverly J. Canham
发明人： Ashay A. Dani , Gudbjorg H. Oskarsdottir , Chris Matayabas, Jr. , Sujit Sharan , Chris L. Rumer , Beverly J. Canham
IPC分类号： H01L21/44 , H01L21/78 , H01L23/544
CPC分类号： H01L21/78 , H01L2224/16 , H01L2924/01019 , H01L2924/10253 , H01L2924/00
摘要： A silicon wafer has a plurality of integrated circuits terminated on a surface of the silicon wafer. The silicon wafer has a soluble protective coat on the surface of the silicon wafer. The coated silicon wafer may be processed by laser scribing. A solvent wash may be used to remove the soluble protective coat and debris from laser scribing. The coated silicon wafer may be saw cut after laser scribing. A flow of solvent may be provided during the saw cutting. The flow of solvent may be sufficient to remove at least a substantial portion of the soluble protective coat.
摘要翻译：硅晶片具有端接在硅晶片表面上的多个集成电路。硅晶片在硅晶片的表面上具有可溶的保护涂层。涂覆的硅晶片可以通过激光划线来加工。可以使用溶剂洗涤剂从激光划线中除去可溶性保护涂层和碎屑。涂覆的硅晶片可以在激光划线之后锯切。在锯切期间可以提供溶剂流。溶剂的流动可能足以除去至少大部分的可溶性保护涂层。

46. 发明授权

US06943107B2 Methods of forming a refractory metal silicide 失效
$Methods of forming a refractory metal silicide$
标题翻译：形成难熔金属硅化物的方法
公开(公告)号：US06943107B2
公开(公告)日：2005-09-13
申请号：US10915935
申请日：2004-08-10
申请人： Gurtej S. Sandhu , Sujit Sharan
发明人： Gurtej S. Sandhu , Sujit Sharan
IPC分类号： H01L21/20 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/44
CPC分类号： H01L21/02667 , C30B1/02 , C30B29/34 , H01L21/2022 , H01L21/28061 , H01L21/28247 , H01L21/28518 , H01L21/32053 , H01L29/7842
摘要： A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material. Where the compressive stress inducing material is provided on the opposite side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is greater than the first phase crystalline material. Example and preferred crystalline phase materials having two phases are refractory metal silicides, such as TiSix.
摘要翻译：形成结晶相材料的方法包括：a）在第一结晶相的结晶材料内部或在其中邻近的第一结晶相中提供应力诱导材料; 和b）在有效地将其转变成第二结晶相的条件下退火第一结晶相的结晶材料。应力诱导材料优选在与第二结晶相退火期间在第一结晶相内诱导压应力，以降低所需的活化能以产生更致密的第二结晶相。示例性压缩应力诱导层包括SiO 2和Si 3 N 4，而用于提供层的应力诱导材料是Ge，W和Co 在压应力诱导材料设置在其上提供结晶相材料的晶片的相同侧上时，其被设置为具有小于第一相结晶材料的热膨胀系数。在压应力诱导材料设置在提供结晶相材料的晶片的相对侧上的情况下，其被设置为具有大于第一相结晶材料的热膨胀系数。具有两相的实例和优选结晶相材料是难熔金属硅化物，例如TiSi x x。

47. 发明授权

US06908849B2 High aspect ratio contact structure with reduced silicon consumption 失效
标题翻译：高纵横比接触结构，降低硅消耗
公开(公告)号：US06908849B2
公开(公告)日：2005-06-21
申请号：US10931854
申请日：2004-09-01
申请人： Ammar Derraa , Sujit Sharan , Paul Castrovillo
发明人： Ammar Derraa , Sujit Sharan , Paul Castrovillo
IPC分类号： H01L21/285 , H01L21/4763 , H01L21/768 , H01L29/45
CPC分类号： H01L21/76846 , H01L21/28518 , H01L21/28556 , H01L21/76843 , H01L21/76855 , H01L21/76868 , H01L21/76877 , H01L29/456
摘要： A high aspect ratio contact structure formed over a junction region in a silicon substrate comprises a titanium interspersed with titanium silicide layer that is deposited in the contact opening and directly contacts an upper surface of the substrate. Silicon-doping of CVD titanium, from the addition of SiH4 during deposition, reduces consumption of substrate silicon during the subsequent silicidation reaction in which the titanium reacts with silicon to form a titanium silicide layer that provides low resistance electrical contacts between the junction region and the silicon substrate. The contact structure further comprises a titanium nitride contact fill that is deposited in the contact opening and fills substantially the entire contact opening.
摘要翻译：形成在硅衬底的接合区域上的高纵横比接触结构包括散布有硅化钛层的钛，其沉积在接触开口中并直接接触衬底的上表面。在沉积期间从SiH 4 Si的添加中CVD钛的掺杂减少了在随后的硅化反应期间底物硅的消耗，其中钛与硅反应形成提供低电阻的硅化钛层接合区域和硅衬底之间的电接触。接触结构还包括氮化钛接触填料，其沉积在接触开口中并基本上填充整个接触开口。

48. 发明申请

US20050109271A1 Method of forming refractory metal silicide 有权
$Method of forming refractory metal silicide$
标题翻译：形成难熔金属硅化物的方法
公开(公告)号：US20050109271A1
公开(公告)日：2005-05-26
申请号：US10975714
申请日：2004-10-27
申请人： Gurtej Sandhu , Sujit Sharan
发明人： Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/20 , H01L21/28 , H01L21/285 , H01L21/3205 , C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14
CPC分类号： H01L21/02667 , C30B1/02 , C30B29/34 , H01L21/2022 , H01L21/28061 , H01L21/28247 , H01L21/28518 , H01L21/32053 , H01L29/7842
摘要： A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material. Where the compressive stress inducing material is provided on the opposite side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is greater than the first phase crystalline material. Example and preferred crystalline phase materials having two phases are refractory metal silicides, such as TiSix.
摘要翻译：形成结晶相材料的方法包括：a）在第一结晶相的结晶材料内部或在其中邻近的第一结晶相中提供应力诱导材料; 和b）在有效地将其转变成第二结晶相的条件下退火第一结晶相的结晶材料。应力诱导材料优选在与第二结晶相退火期间在第一结晶相内诱导压应力，以降低所需的活化能以产生更致密的第二结晶相。示例性压缩应力诱导层包括SiO 2和Si 3 N 4，而用于提供层的应力诱导材料是Ge，W和Co 在压应力诱导材料设置在其上提供结晶相材料的晶片的相同侧上时，其被设置为具有小于第一相结晶材料的热膨胀系数。在压应力诱导材料设置在提供结晶相材料的晶片的相对侧上的情况下，其被设置为具有大于第一相结晶材料的热膨胀系数。具有两相的实例和优选结晶相材料是难熔金属硅化物，例如TiSi x x。

49. 发明授权

US06773502B2 Method of forming a crystalline phase material 失效
标题翻译：形成结晶相材料的方法
公开(公告)号：US06773502B2
公开(公告)日：2004-08-10
申请号：US10300482
申请日：2002-11-19
申请人： Gurtej S. Sandhu , Sujit Sharan
发明人： Gurtej S. Sandhu , Sujit Sharan
IPC分类号： C30B2502
CPC分类号： H01L21/02667 , C30B1/02 , C30B29/34 , H01L21/2022 , H01L21/28061 , H01L21/28247 , H01L21/28518 , H01L21/32053 , H01L29/7842
摘要： Methods of forming an electrically conductive line include providing a stress inducing material within or a compressive stress inducing layer operatively adjacent a crystalline material of a first crystalline phase. In addition, such methods include annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. Some methods also include providing stress inducing materials into a refractory metal layer. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials include Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material. Example and preferred crystalline phase materials having two phases are refractory metal silicides, such as TiSix.
摘要翻译：形成导电线的方法包括在与第一结晶相的结晶材料可操作地相邻处提供应力诱导材料或压应力诱导层。此外，这些方法包括在有效地将其转变为第二结晶相的条件下退火第一结晶相的结晶材料。一些方法还包括将应力诱导材料提供到难熔金属层中。示例性压缩应力诱导层包括SiO 2和Si 3 N 4，而示例的应力诱导材料包括Ge，W和Co。当压应力诱导材料设置在提供结晶相材料的晶片的同一侧时，具有小于第一相结晶材料的热膨胀系数。具有两相的实例和优选结晶相材料是难熔金属硅化物，例如TiSix。

50. 发明授权

US06737328B1 Methods of forming silicon dioxide layers, and methods of forming trench isolation regions 有权
标题翻译：形成二氧化硅层的方法以及形成沟槽隔离区的方法
公开(公告)号：US06737328B1
公开(公告)日：2004-05-18
申请号：US09497080
申请日：2000-02-02
申请人： Sujit Sharan , Gurtej S. Sandhu
发明人： Sujit Sharan , Gurtej S. Sandhu
IPC分类号： H01L2120
CPC分类号： H01L21/02164 , C23C16/045 , C23C16/402 , H01L21/02211 , H01L21/02274 , H01L21/31612 , H01L21/76224
摘要： In one aspect, the invention includes a method of forming a, silicon dioxide layer, including: a) forming a high density plasma proximate a substrate, the plasma including silicon dioxide precursors; b) forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and c) while depositing, etching the deposited silicon dioxide with the plasma at an, etch rate; a ratio of the deposition rate to the etch rate being at least: about 4:1. In another aspect, the invention includes a method of forming a silicon dioxide layer, including: a) forming a high density plasma proximate a substrate; b) flowing gases into the plasma, at least some of the gases forming silicon dioxide; c) depositing the silicon dioxide formed from the gases over the substrate; and d) while depositing the silicon dioxide, maintaining a temperature of the substrate at greater than or equal to about 500° C. In yet another aspect, the invention includes a method of forming a silicon dioxide layer, including: a) forming a high density plasma proximate a substrate; b) flowing gases into the plasma, at least some of the gases forming silicon dioxide; c) depositing the silicon dioxide formed from the gases over the substrate; and d) not cooling the substrate with a coolant gas while depositing the silicon dioxide.
摘要翻译：一方面，本发明包括形成二氧化硅层的方法，包括：a）在基底附近形成高密度等离子体，所述等离子体包括二氧化硅前体; b）从前体形成二氧化硅，二氧化硅以沉积速率沉积在衬底上; 和c）在沉积时，以蚀刻速率用等离子体蚀刻沉积的二氧化硅; 沉积速率与蚀刻速率的比率为至少约4:1。另一方面，本发明包括形成二氧化硅层的方法，包括：a）在基底附近形成高密度等离子体; b）将气体流入等离子体，至少一些形成二氧化硅的气体; c）将由气体形成的二氧化硅沉积在衬底上; 和d）同时沉积二氧化硅，保持基板的温度大于或等于约500℃。另一方面，本发明包括形成二氧化硅层的方法，包括：a）形成高的靠近基底的密度等离子体; b）将气体流入等离子体，至少一些形成二氧化硅的气体; c）将由气体形成的二氧化硅沉积在衬底上; 和d）在沉积二氧化硅的同时不用冷却剂气体冷却衬底。

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