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41. 发明授权

US07904655B2 Branching memory-bus module with multiple downlink ports to standard fully-buffered memory modules 有权
标题翻译：将具有多个下行链路端口的内存总线模块分支到标准的全缓冲内存模块
公开(公告)号：US07904655B2
公开(公告)日：2011-03-08
申请号：US12115200
申请日：2008-05-05
申请人： Ramon S. Co
发明人： Ramon S. Co
IPC分类号： G06F13/28
CPC分类号： G06F13/1684 , G06F13/1673 , G11C5/04 , Y02D10/14
摘要： A branching memory-bus module has one uplink port and two or more downlink ports. Frames sent downstream by a host processor are received on the uplink port and repeated to the multiple downlink ports to two or more branches of memory modules. Frames sent upstream to the processor by a memory module on a downlink port are repeated to the uplink port. A branching Advanced Memory Buffer (AMB) on the branching memory-bus module has re-timing and re-synchronizing buffers that repeat frames to the multiple downlink ports. Elastic buffers can merge and synchronize frames from different downlink branches. Separate northbound and southbound lanes may be replaced by bidirectional lanes to reduce pin counts. Latency from the host processor to the farthest memory module is reduced by branching compared with a serial daisy-chain of fully-buffered memory modules. Point-to-point bus segments have only two endpoints despite branching by the branching AMB.
摘要翻译：分支存储器总线模块具有一个上行链路端口和两个或更多个下行链路端口。在主机处理器发送的下游的帧在上行链路端口上被接收并且被重复到多个下行链路端口到存储器模块的两个或更多个分支。通过下行链路端口上的存储器模块向处理器上行发送的帧被重复到上行链路端口。分支存储器总线模块上的分支高级存储器缓冲器（AMB）具有对多个下行链路端口重复帧的重新定时和重新同步缓冲器。弹性缓冲区可以合并和同步来自不同下行链路分支的帧。分开的北行和南行车道可以由双向车道代替，以减少销数。与串行菊花链完全缓冲的内存模块相比，从主处理器到最远的内存模块的延迟减少了。点对点总线段只有两个端点，尽管分支AMB分支。

42. 发明申请

US20110050268A1 Parking Structure Memory-Module Tester that Moves Test Motherboards Along a Highway for Remote Loading/Unloading 有权
公开(公告)号：US20110050268A1
公开(公告)日：2011-03-03
申请号：US12941196
申请日：2010-11-08
申请人： Ramon S. Co , Kevin J. Sun
发明人： Ramon S. Co , Kevin J. Sun
IPC分类号： G01R31/20
CPC分类号： G11C29/56 , G11C29/56016
摘要： A parking-structure test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. An unloader removes tested memory modules from test sockets on the motherboards, and a loader inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader to a parking and testing structure. An elevator raises or lowers the motherboards to different parking levels in the parking and testing structure. The motherboards move from the elevator to test stations on the parking level. A retractable connector from the test station makes contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns via the elevator and conveyors.

43. 发明授权

US07797578B2 Fault diagnosis of serially-addressed memory chips on a test adaptor board to a middle memory-module slot on a PC motherboard 有权
标题翻译：将测试适配器板上的串行存储芯片故障诊断到PC主板上的中间存储模块插槽
公开(公告)号：US07797578B2
公开(公告)日：2010-09-14
申请号：US12101138
申请日：2008-04-10
申请人： Ramon S. Co
发明人： Ramon S. Co
IPC分类号： G06F11/00
CPC分类号： G11C29/56 , G11C5/04 , G11C29/56008 , G11C29/56016
摘要： A standard memory module socket is removed from a target DRAM module slot on the component side and the test adaptor board connects to the target DRAM module slot on the reverse (solder) side of a personal computer motherboard, or an extender card may be used. The target DRAM module slot is a middle slot, such as the second or third of four DRAM module slots. The first and fourth DRAM module slots are populated with known good memory modules storing the BIOS at a high address and an operating system image and a test program at a low address. The test program accesses a memory chip in a test socket on a test adaptor board that is connected to the target DRAM module slot to locate defects. The motherboard does not crash since the BIOS, OS image, and test program are not stored in the memory chip under test.
摘要翻译：标准内存模块插座从组件侧的目标DRAM模块插槽中移除，测试适配器板连接到个人计算机主板背面（焊接）侧的目标DRAM模块插槽，或者可以使用扩展卡。目标DRAM模块插槽是中间插槽，例如四个DRAM模块插槽的第二或第三。第一和第四DRAM模块插槽用已知的良好存储器模块填充存储在高地址处的BIOS，操作系统映像和低地址处的测试程序。测试程序访问连接到目标DRAM模块插槽的测试适配器板上的测试插座中的存储芯片，以定位缺陷。主板不会崩溃，因为BIOS，OS映像和测试程序未被存储在被测芯片内。

44. 发明申请

US20100213027A1 Conveyor-Based Memory-Module Tester with Elevators Distributing Moving Test Motherboards Among Parallel Conveyors For Testing 有权
标题翻译：基于输送机的存储模块测试仪与电梯分布平行输送机中的移动测试主板进行测试
公开(公告)号：US20100213027A1
公开(公告)日：2010-08-26
申请号：US12392387
申请日：2009-02-25
申请人： Ramon S. Co , Kevin J. Sun
发明人： Ramon S. Co , Kevin J. Sun
IPC分类号： B65G37/00 , G06F11/07
CPC分类号： G11C29/56 , B65G47/71 , G11C5/04 , G11C29/56016
摘要： A conveyor-stack test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. A loader-unloader removes tested memory modules from test sockets on the motherboards and inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader-unloader to an elevator. The elevator raises or lowers the motherboards to different levels in a conveyor stack with multiple levels of conveyors each with many test stations. The motherboards move along conveyors in the conveyor stack until reaching test stations. A retractable connector from the test station extends to make contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns.
摘要翻译：输送机堆叠测试系统具有测试内存模块的主板。主板不是静止的，而是位于沿传送带移动的活动托盘内。装载机卸载程序从主板上的测试插槽中删除测试的内存模块，并使用机械臂将未经测试的内存模块插入主板。输送机将主板从装载机卸载机运送到电梯。电梯将主板升高或降低到输送机堆叠中的不同水平，多层输送机各有许多测试站。主板沿着输送机堆栈中的输送机移动，直至到达测试站。来自测试站的可伸缩连接器延伸以与主板连接器接触，以对主板供电，然后测试存储器模块。测试结果从测试台传送到主机控制器，主机控制器指示装载机卸载机在主板返回后对测试的内存模块进行排序。

45. 发明申请

US20090217093A1 Fault Diagnosis of Serially-Addressed Memory Modules on a PC Motherboard 有权
标题翻译： PC主板上串行存储器模块的故障诊断
公开(公告)号：US20090217093A1
公开(公告)日：2009-08-27
申请号：US12036985
申请日：2008-02-25
申请人： Ramon S. Co
发明人： Ramon S. Co
IPC分类号： G06F11/00
CPC分类号： G06F11/2733 , G01R31/31723 , G01R31/31905 , G11C5/04 , G11C29/56 , G11C29/56016 , G11C2029/5602
摘要： A test adaptor board connects to a personal computer (PC) motherboard that tests a memory module in a test socket. A standard memory module socket is removed from a target DRAM module slot on the component side and the test adaptor board connects to the target DRAM module slot on the reverse (solder) side of the motherboard. The target DRAM module slot is a middle slot, such as the second or third of four DRAM module slots. The first and fourth DRAM module slots are populated with known good memory modules storing the BIOS at a high address and an operating system image and a test program at a low address. The test program accesses a memory module in the test socket to locate defects. The motherboard does not crash since the BIOS, OS image, and test program are not stored in the memory module under test.
摘要翻译：测试适配器板连接到测试测试插座中的内存模块的个人计算机（PC）主板。从组件侧的目标DRAM模块插槽中移除标准内存模块插座，测试适配器板连接到主板背面（焊锡）侧的目标DRAM模块插槽。目标DRAM模块插槽是中间插槽，例如四个DRAM模块插槽的第二或第三。第一和第四DRAM模块插槽用已知的良好存储器模块填充存储在高地址处的BIOS，操作系统映像和低地址处的测试程序。测试程序访问测试套接字中的内存模块来定位缺陷。主板不会崩溃，因为BIOS，OS映像和测试程序未存储在被测内存模块中。

46. 发明授权

US06742144B2 Local heating of memory modules tested on a multi-motherboard tester 有权
标题翻译：在多主板测试仪上测试的内存模块的本地加热
公开(公告)号：US06742144B2
公开(公告)日：2004-05-25
申请号：US09683525
申请日：2002-01-14
申请人： Ramon S. Co
发明人： Ramon S. Co
IPC分类号： H02H305
CPC分类号： G11C29/56016 , G01R31/01 , G01R31/31713 , G01R31/31905 , G11C5/04 , G11C29/028 , G11C29/56 , G11C2029/5004 , H05K1/141
摘要： A test system has many motherboards. Each motherboard has a reverse-mounted test adaptor board that contains a test socket. A robotic arm inserts a memory module into the test socket, allowing the motherboard to execute programs to test the memory module. A test chamber surrounds the test socket. Compressed air is regulated and routed to local heaters near each motherboard. The local heaters pass the air over a resistive heating element to heat the air. The heated air is then directed into the test chamber to heat the memory module being tested. A local valve controls the air flow through the local heater. A host computer receives temperature measurements from each test chamber and adjusts the local heater and valve to maintain a desired test temperature. The motherboards can be cooled by cooling fans while the memory modules being tested are heated.
摘要翻译：测试系统有很多主板。每个主板都有一个反向安装的测试适配器板，其中包含测试插座。机器手臂将内存模块插入测试插座，允许主板执行程序来测试内存模块。测试室围绕测试插座。压缩空气被调节并传送到每个主板附近的本地加热器。本地加热器将空气通过电阻加热元件以加热空气。然后将加热的空气引导到测试室中以加热被测试的存储器模块。局部阀控制通过本地加热器的气流。主机接收每个测试室的温度测量值，并调节本地加热器和阀门以保持所需的测试温度。当测试的存储器模块被加热时，主板可以被冷却风扇冷却。

47. 发明授权

US06240101B1 Bi-directional daisy-chain cascading of network repeaters 失效
标题翻译：网络转发器的双向菊花链级联
公开(公告)号：US06240101B1
公开(公告)日：2001-05-29
申请号：US09082002
申请日：1998-05-20
申请人： Ramon S. Co , Daniel Hsu
发明人： Ramon S. Co , Daniel Hsu
IPC分类号： H04L2520
CPC分类号： H04L25/20
摘要： Each stacked repeater has two activity ports that are daisy chained to the activity ports of other repeaters in the stack. Each activity port has an input and an output. The two activity ports connect to the next repeater above and the next repeater below in the stack. Each repeater examines its local network ports to computer stations such as PC's to determine if any are inputting data to the repeater. When any local port is inputting data, the repeater activates both of its activity-port outputs. When no local port is inputting data, the repeater simply passes each activity-port's input through to the other activity-port's output. Thus the activity-port output indicates when either the repeater or an earlier repeater in the chain has a local port inputting data. Port activity is chained in two directions: through all repeaters in the stack from the top-most repeater, down the stack to the bottom-most repeater, and also from the bottom-most repeater, up through the repeaters to the top-most repeater. Thus one activity-port's input indicates when any of the repeaters above have a local port inputting data, while the other activity-port's input indicates when any of the repeaters below have a local port inputting data. The one-port-left state is determined by any repeater using the two activity ports.
摘要翻译：每个堆叠中继器有两个活动端口，菊花链连接到堆叠中其他中继器的活动端口。每个活动端口都有一个输入和一个输出。两个活动端口连接到上面的下一个中继器和下面的堆叠中的中继器。每个中继器将其本地网络端口检测到PC等电脑站，以确定是否有任何数据向中继器输入。当任何本地端口正在输入数据时，中继器激活其两个活动端口输出。当本地端口没有输入数据时，中继器只需将每个活动端口的输入通过另一个活动端口的输出。因此，活动端口输出指示链中的中继器或较早的中继器何时具有本地端口输入数据。端口活动在两个方向链接：通过堆叠中最上层中继器的所有中继器，堆叠到最底层的中继器，以及最底层的中继器，直到中继器到最上层的中继器。因此，一个活动端口的输入指示何时上述任何中继器具有本地端口输入数据，而另一个活动端口的输入指示何时下列任何转发器具有本地端口输入数据。单端口左状态由任何使用两个活动端口的中继器确定。

48. 发明授权

US5834950A Phase detector which eliminates frequency ripple 失效
标题翻译：消除频率纹波的相位检测器
公开(公告)号：US5834950A
公开(公告)日：1998-11-10
申请号：US214376
申请日：1994-03-17
申请人： Ramon S. Co , Richard L. Traber
发明人： Ramon S. Co , Richard L. Traber
IPC分类号： H03L7/089 , H04L7/033 , H03K5/26
CPC分类号： H04L7/033 , H03L7/089
摘要： A phase detector is disclosed that eliminates frequency ripple in a phase-locked loop circuit. The detector includes first and second circuits for providing UP and DOWN signals respectively. It also includes a delay element for setting the duration of the DOWN signal so as to eliminate phase jitter and static phase offset.
摘要翻译：公开了消除锁相环电路中的频率纹波的相位检测器。检测器包括分别提供UP和DOWN信号的第一和第二电路。它还包括用于设置DOWN信号的持续时间的延迟元件，以消除相位抖动和静态相位偏移。

49. 发明授权

US5459753A Method and apparatus for pattern independent phase detection and timing recovery 失效
标题翻译：用于图形独立相位检测和定时恢复的方法和装置
公开(公告)号：US5459753A
公开(公告)日：1995-10-17
申请号：US880172
申请日：1992-05-06
申请人： Ramon S. Co , Ron Kao
发明人： Ramon S. Co , Ron Kao
IPC分类号： H04L7/033 , H04L7/04 , H04L25/49 , H04L7/00
CPC分类号： H04L25/4904 , H04L7/042 , H04L7/033
摘要： A timing recovery scheme disposed to be substantially invariant to the specific composition of an input data sequence. The phase detection network of the present invention will typically be addressed by a data waveform having a plurality of data packets separated by data delimiters. In operation, the phase detection network of the present invention generates a phase error signal in response to the phase difference between a binary data waveform and a periodic clock waveform recovered therefrom. The inventive phase detection network includes a shift register for storing samples of the incident data waveform. The contents of the shift register are monitored by a boundary detection circuit disposed to signal the presence of one of the delimiters within the shift register. Upon detection of such a delimiter a boundary correction circuit is disposed to generate a phase detection enable signal. The inventive phase detection network further includes a phase detector which is operative, upon being enabled by the boundary correction circuit, to compare the relative phase between the data and clock waveforms in order to synthesize the phase error signal.
摘要翻译：定时恢复方案被设置为基本上不变于输入数据序列的具体组成。本发明的相位检测网络通常将由具有由数据分隔符分隔的多个数据分组的数据波形来解决。在操作中，本发明的相位检测网络响应于二进制数据波形和从其恢复的周期性时钟波形之间的相位差产生相位误差信号。本发明的相位检测网络包括用于存储入射数据波形的样本的移位寄存器。移位寄存器的内容由边界检测电路监视，该边界检测电路用于发信号通知移位寄存器内的一个定界符的存在。当检测到这样的定界符时，设置边界校正电路以产生相位检测使能信号。本发明的相位检测网络还包括一个相位检测器，它在由边界校正电路使能时可操作，以比较数据和时钟波形之间的相对相位，以便合成相位误差信号。

50. 发明授权

US08035408B1 Socket fixture for testing warped memory modules on a PC motherboard 有权
标题翻译：用于在PC主板上测试翘曲的内存模块的套筒夹具
公开(公告)号：US08035408B1
公开(公告)日：2011-10-11
申请号：US12965693
申请日：2010-12-10
申请人： Ramon S. Co
发明人： Ramon S. Co
IPC分类号： G01R31/00 , H01R13/15
CPC分类号： G11C29/56 , G01R1/0466 , G11C5/04 , G11C29/56016 , G11C2029/5602
摘要： A memory module test socket can accept modules with bent or warped printed-circuit boards (PCBs). A support plate is mounted above a Personal Computer (PC) motherboard by standoffs. An extender card fits through a slot in the support plate. The bottom edge of the extender card is plugged into a motherboard memory module socket on the motherboard. The top of the extender card has an extender socket that sits atop the support plate. End guides are mounted to the support plate and clamp down the extender socket. Funnel guides formed in the end guides have a funnel shape to guide ends of a memory module for better alignment when inserted into the extender socket. A pusher plate with a triangular guide or a perpendicular rod applies a perpendicular force on the middle of a warped memory module to align the middle to the extender socket during insertion.
摘要翻译：内存模块测试插座可以接受带弯曲或翘曲的印刷电路板（PCB）的模块。支撑板通过支座安装在个人计算机（PC）主板上方。扩展卡通过支撑板中的槽插入。扩展卡的底部边缘插入主板上的主板内存模块插槽。扩展卡的顶部有一个位于支撑板上方的扩展插座。端部导向件安装到支撑板上并夹紧扩展器插座。形成在端部导向件中的漏斗引导件具有漏斗形状，以引导存储器模块的端部，以便在插入扩展器插座时更好地对准。具有三角形引导件或垂直杆的推动板在翘曲的存储器模块的中间施加垂直的力，以在插入期间将中间对准扩展器插座。

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