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41. 发明授权

US08230162B2 Block management method for flash memory, and flash memory controller and flash memory storage device using the same 有权
标题翻译：闪存的块管理方法，闪存控制器和闪存存储设备使用相同
公开(公告)号：US08230162B2
公开(公告)日：2012-07-24
申请号：US12705325
申请日：2010-02-12
申请人： Hsiang-Hsiung Yu , Yi-Hsiang Huang , Chung-Lin Wu , Yu-Chung Shen
发明人： Hsiang-Hsiung Yu , Yi-Hsiang Huang , Chung-Lin Wu , Yu-Chung Shen
IPC分类号： G06F12/14
CPC分类号： G06F21/6209
摘要： A block management method for managing blocks of a flash memory storage device is provided. The flash memory storage device includes a flash memory controller. The block management method includes the following steps. At least a part of the blocks is grouped into a first partition and a second partition. Whether an authentication code exists is determined. When the authentication code exists, the blocks belonging to the first partition are provided for a host system to access, so the host system displays the first partition and hides the second partition. An authentication information is received from the host system. Whether the authentication information and the authentication code are identical is authenticated. When the authentication information and the authentication code are identical, the blocks belonging to the second partition are provided for the host system to access, so the host system displays the second partition and hides the first partition.
摘要翻译：提供一种用于管理闪存存储设备的块的块管理方法。闪存存储设备包括闪存控制器。块管理方法包括以下步骤。至少一部分块被分组成第一分区和第二分区。确定是否存在认证码。当认证码存在时，属于第一分区的块被提供给主机系统进行访问，因此主机系统显示第一个分区并隐藏第二个分区。从主机系统接收认证信息。认证信息和验证码是否相同是否通过认证。当认证信息和认证码相同时，属于第二分区的块被提供给主机系统访问，所以主机系统显示第二分区并隐藏第一分区。

42. 发明授权

US08058732B2 Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same 失效
标题翻译：用于晶圆级芯片尺寸封装的半导体晶片结构，用于使用它们的功率器件，封装和系统及其制造方法
公开(公告)号：US08058732B2
公开(公告)日：2011-11-15
申请号：US12275086
申请日：2008-11-20
申请人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Ihsiu Ho , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Rohit Dikshit
发明人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Ihsiu Ho , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Rohit Dikshit
IPC分类号： H01L23/48
CPC分类号： H01L29/7802 , H01L23/3114 , H01L23/36 , H01L23/482 , H01L24/16 , H01L24/19 , H01L24/31 , H01L29/0657 , H01L2224/04105 , H01L2224/20 , H01L2224/73253 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/351 , H01L2924/00
摘要： Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.
摘要翻译：公开了半导体管芯结构，其使具有垂直功率器件的管芯封装在晶片级芯片级封装中，其中导电端子存在于管芯的一个表面处，并且器件具有非常低的导通状态抵抗性。在示例性实施例中，沟槽和孔形成在管芯的背面，孔与导管的顶表面处的导电区接触。可以在沟槽和孔上设置导电层和/或导体，以将器件的背面导电电极电耦合到导电区域。还公开了使用根据本发明的具有模具结构的模具的封装和系统，以及根据本发明的具有模具结构的模具的方法。

43. 发明申请

US20110124158A1 THERMAL ENHANCED UPPER AND DUAL HEAT SINK EXPOSED MOLDED LEADLESS PACKAGE 失效
标题翻译：热增强型和双重散热模具无铅包装
公开(公告)号：US20110124158A1
公开(公告)日：2011-05-26
申请号：US13019488
申请日：2011-02-02
申请人： Chung-Lin Wu , Rajeev D. Joshi
发明人： Chung-Lin Wu , Rajeev D. Joshi
IPC分类号： H01L21/56
CPC分类号： H01L21/561 , H01L21/4828 , H01L23/4334 , H01L23/49548 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2221/68377 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49113 , H01L2224/73265 , H01L2224/83 , H01L2224/85 , H01L2224/92247 , H01L2224/97 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.
摘要翻译：半导体封装包括半导体器件30和模制的上部散热器10.散热器具有面向半导体器件的内表面16和至少部分地暴露于封装器件周围环境的外表面15。环形平面基座11围绕凸出或突出的中心区域12.该区域由基座11的平面支承在四个倾斜壁13.1-13.4之上。壁相对于平面环形基座呈锐角倾斜，并朝向上散热片10的中心倾斜。环形基座11的外周围是四个支撑臂18.1-18.4。支撑臂相对于平面环形基座11的内表面16以钝角设置。

44. 发明申请

US20090261461A1 SEMICONDUCTOR PACKAGE WITH LEAD INTRUSIONS 审中-公开
标题翻译：半导体封装与引线插入
公开(公告)号：US20090261461A1
公开(公告)日：2009-10-22
申请号：US12104182
申请日：2008-04-16
申请人： Steven Sapp , Chung-Lin Wu , Maria Christina B. Estacio , Bigildis Dosdos , Hamza Yilmaz
发明人： Steven Sapp , Chung-Lin Wu , Maria Christina B. Estacio , Bigildis Dosdos , Hamza Yilmaz
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/49562 , H01L23/49524 , H01L23/49548 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/37147 , H01L2224/45014 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48095 , H01L2224/4813 , H01L2224/48247 , H01L2224/4846 , H01L2224/48472 , H01L2224/48599 , H01L2224/48699 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/73265 , H01L2224/84801 , H01L2224/8485 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599 , H01L2924/206
摘要： Semiconductor packages comprising a plurality of lead fingers containing a lead intrusion at the edge of the lead fingers are described. The semiconductor packages comprise an integrated circuit chip that is connected to a die pad and is electrically connected to multiple lead fingers. One or more of the lead fingers may have a lead intrusion disposed on the external exposed lower surface of the lead finger. The lead intrusion may have a height that is about ⅕ to about ½ the height of a lead finger, a width that is about ⅕ to about 1/2 the width of a lead finger, and a depth that is about ¼ to about ¾ the length of the externally exposed lower surface of a lead finger. The lead intrusion increases the area on the lead finger that contacts a bond material, such as solder, and therefore increase the strength of the joint between the semiconductor package and an external surface to which the lead finger is connected (i.e., a PCB). The lead intrusion allows out gassing during reflow of the bond material which may reduce voiding. The lead intrusion can also increase bond joint reliability by providing longer crack propagation length.
摘要翻译：描述了包括在引线的边缘处包含铅侵入的多个引线指的半导体封装。半导体封装包括连接到管芯焊盘并且电连接到多个引线指的集成电路芯片。一个或多个引导指可以具有设置在引线指的外部暴露下表面上的引线侵入。引线入侵可以具有引导指的高度的约1/5至约1/2的高度，宽度是引线指的宽度的大约1/5至大约1/2，并且深度约为1/4 到铅笔的外部暴露的下表面的长度的约3/4。引线入侵增加了引线接触诸如焊料的接合材料的引线区域，因此增加了半导体封装与引线指连接的外表面（即PCB）之间的接合强度。铅侵入允许在回流焊接材料期间放气，这可能减少空隙。铅侵入也可以通过提供更长的裂纹扩展长度来增加接合点的可靠性。

45. 发明申请

US20090165537A1 Device and method for optical nanoindentation measurement 有权
标题翻译：光学纳米压痕测量的装置和方法
公开(公告)号：US20090165537A1
公开(公告)日：2009-07-02
申请号：US12230340
申请日：2008-08-28
申请人： Jiong-Shiun Hsu , Hui-Ching Lu , Chung-Lin Wu , Sheng-Jui Chen
发明人： Jiong-Shiun Hsu , Hui-Ching Lu , Chung-Lin Wu , Sheng-Jui Chen
IPC分类号： G01N3/48
CPC分类号： G01N3/405 , G01N2203/0286 , G01N2203/0641 , G01Q60/366
摘要： This invention relates to a device and method for optical nanoindentation measurement, according to which respective measurement results are obtained by having an indenter tip apply load to a fixed portion of a thin film, having an indenter tip apply load to a non-fixed portion of a thin film, and having a vibrating component transmit the dynamic properties of the vibration to the thin film. By combining the above measurement results in calculations, the Young's modulus, the Poisson's ratio, and the density of the thin film can be obtained.
摘要翻译：本发明涉及一种用于光学纳米压痕测量的装置和方法，根据该装置和方法，通过将压头施加载荷施加到薄膜的固定部分上，获得各自的测量结果，该固定部分具有压头施加载荷到非固定部分并且具有振动分量的薄膜将振动的动态特性传递给薄膜。通过在计算中结合上述测量结果，可以获得杨氏模量，泊松比和薄膜的密度。

46. 发明申请

US20140042599A1 MULTI-CHIP MODULE POWER CLIP 有权
标题翻译：多芯片模块电源夹
公开(公告)号：US20140042599A1
公开(公告)日：2014-02-13
申请号：US13584015
申请日：2012-08-13
申请人： Chung-Lin Wu , Steven Sapp , Bigildis Dosdos , Suresh Belani , Sunggeun Yoon
发明人： Chung-Lin Wu , Steven Sapp , Bigildis Dosdos , Suresh Belani , Sunggeun Yoon
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/4334 , H01L23/3107 , H01L23/49524 , H01L23/49541 , H01L23/49548 , H01L23/49562 , H01L23/49575 , H01L24/16 , H01L29/4236 , H01L29/42372 , H01L29/7813 , H01L29/7828 , H01L2224/13147 , H01L2224/16245 , H01L2224/48137 , H01L2224/48247 , H01L2924/13091 , H01L2924/15747 , H01L2924/30107 , H01L2924/00 , H01L2924/00014
摘要： The multi-chip leadless module 200 has integrated circuit (IC) 150, dual re-channel mosfet 110, IC leads 210, 211, 212, gate leads 213, 213, and source leads 217-220 encapsulated in resin 250. The IC 150 and the dual n-channel mosfet 110 are mounted face down on the leads. IC leads 210, 211, 212 are made of planar metal and connect, respectively, to the electrodes TEST, VDD and VM on the IC 150 using a flip chip technique to assemble the leads on copper pillars or copper studs.
摘要翻译：多芯片无引线模块200具有集成电路（IC）150，双重信道mosfet 110，IC引线210,211,212，栅极引线213,213和封装在树脂250中的源极引线217-220。IC 150 并且双n沟道MOSFET 110面朝下安装在引线上。 IC引线210,211,212由平面金属制成，并且使用倒装芯片技术分别连接到IC 150上的电极TEST，VDD和VM，以将铜柱或铜螺柱上的引线组装。

47. 发明申请

US20130132640A1 DATA WRITING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME 有权
标题翻译：数据写入方法，以及使用该存储器的存储器控制器和存储器存储装置
公开(公告)号：US20130132640A1
公开(公告)日：2013-05-23
申请号：US13366271
申请日：2012-02-04
申请人： Chung-Lin Wu , Yi-Hsiang Huang
发明人： Chung-Lin Wu , Yi-Hsiang Huang
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7203 , G06F2212/7205
摘要： A data writing method for a rewritable non-volatile memory module, and a memory controller and a memory storage apparatus using the same are provided. The method includes partitioning physical blocks of the rewritable non-volatile memory module into a data area and a spare area and configuring logical blocks. The method also includes selecting physical blocks from the spare area as spare physical blocks corresponding to a logical block and using only lower physical pages of the spare physical blocks to store updated data that is to be written into the logical block. The method further includes moving valid data of all logical pages of the logical block into a physical block of the data area, wherein each lower physical page and an upper physical page corresponding thereto in the physical block are programmed together. Accordingly, the method can effectively improve the speed and reliability of writing data.
摘要翻译：提供了一种用于可重写非易失性存储器模块的数据写入方法，以及存储器控制器和使用其的存储器存储装置。该方法包括将可重写非易失性存储器模块的物理块划分为数据区和备用区并配置逻辑块。该方法还包括从备用区选择物理块作为对应于逻辑块的备用物理块，并且仅使用备用物理块的较低物理页来存储要写入逻辑块的更新数据。该方法还包括将逻辑块的所有逻辑页的有效数据移动到数据区的物理块中，其中在物理块中与之对应的每个下部物理页和上部物理页一起编程。因此，该方法可以有效地提高写入数据的速度和可靠性。

48. 发明授权

US08278742B2 Thermal enhanced upper and dual heat sink exposed molded leadless package and method 失效
标题翻译：热增强型上，下两个散热片裸露无铅封装及方法
公开(公告)号：US08278742B2
公开(公告)日：2012-10-02
申请号：US13019488
申请日：2011-02-02
申请人： Chung-Lin Wu , Rajeev D. Joshi
发明人： Chung-Lin Wu , Rajeev D. Joshi
IPC分类号： H01L23/495 , H01L23/10 , H01L23/34 , H01L23/28
CPC分类号： H01L21/561 , H01L21/4828 , H01L23/4334 , H01L23/49548 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2221/68377 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49113 , H01L2224/73265 , H01L2224/83 , H01L2224/85 , H01L2224/92247 , H01L2224/97 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.
摘要翻译：半导体封装包括半导体器件30和模制的上部散热器10.散热器具有面向半导体器件的内表面16和至少部分地暴露于封装器件周围环境的外表面15。环形平面基座11围绕凸出或突出的中心区域12.该区域由基座11的平面支承在四个倾斜壁13.1-13.4之上。壁相对于平面环形基座呈锐角倾斜，并朝向上散热片10的中心倾斜。环形基座11的外周围是四个支撑臂18.1-18.4。支撑臂相对于平面环形基座11的内表面16以钝角设置。

49. 发明申请

US20110230046A1 SEMICONDUCTOR DICE WITH BACKSIDE TRENCHES FILLED WITH ELASTIC MATERIAL FOR IMPROVED ATTACHMENT, PACKAGES USING THE SAME, AND METHODS OF MAKING THE SAME 有权
标题翻译：具有用于改进附件的用弹性材料填充的背面斜面的半导体切片，使用其的包装及其制造方法
公开(公告)号：US20110230046A1
公开(公告)日：2011-09-22
申请号：US13151495
申请日：2011-06-02
申请人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
发明人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
IPC分类号： H01L21/28
CPC分类号： H01L23/49513 , H01L23/49524 , H01L24/05 , H01L24/16 , H01L24/32 , H01L24/33 , H01L24/40 , H01L24/48 , H01L24/73 , H01L24/83 , H01L29/0657 , H01L2224/0401 , H01L2224/04026 , H01L2224/04042 , H01L2224/05555 , H01L2224/05556 , H01L2224/13099 , H01L2224/16 , H01L2224/2518 , H01L2224/291 , H01L2224/29111 , H01L2224/29139 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73255 , H01L2224/73265 , H01L2224/83856 , H01L2224/92247 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/10158 , H01L2924/10253 , H01L2924/13091 , H01L2924/351 , H01L2924/00 , H01L2924/0105 , H01L2924/3512 , H01L2224/45099 , H01L2224/05599 , H01L2224/37099
摘要： Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.
摘要翻译：公开了具有填充有弹性导电材料的背面沟槽的半导体裸片。沟槽减小了掺入骰子的器件的导通电阻。弹性导电材料为模具的背面提供导电路径，在半导体芯片上由热循环引起的微小应力。还公开了使用骰子的包裹以及制造骰子的方法。

50. 发明申请

US20110066818A1 STORAGE DEVICE, MEMORY CONTROLLER, AND DATA PROTECTION METHOD 有权
标题翻译：存储设备，存储器控制器和数据保护方法
公开(公告)号：US20110066818A1
公开(公告)日：2011-03-17
申请号：US12822385
申请日：2010-06-24
申请人： Hsiang-Hsiung Yu , Chung-Lin Wu , Yi-Hsiang Huang , Yu-Chung Shen
发明人： Hsiang-Hsiung Yu , Chung-Lin Wu , Yi-Hsiang Huang , Yu-Chung Shen
IPC分类号： G06F12/14 , G06F12/00 , G06F12/16
CPC分类号： G06F21/10 , G06F21/78
摘要： A storage device, a memory controller, and a data protection method are provided. The method includes when receiving a read command sent by a host, adopting a corresponding output flow rate limit to determine an operation that is executed on read data corresponding to the read command by the host according to location information included in the read command or a type of a transmission interface between the host and the storage device. The method also includes executing an interference procedure by the storage device to prevent the read data from being copied to the host or slow down the speed of copying the read data to the host when identifying that the operation is a copy operation.
摘要翻译：提供存储装置，存储器控制器和数据保护方法。该方法包括当接收到主机发送的读取命令时，采用相应的输出流量限制，以根据包括在读取命令中的位置信息或类型的类型来确定对主机对应于读取命令的读取数据执行的操作主机和存储设备之间的传输接口。该方法还包括执行存储设备的干扰过程，以防止读取数据被复制到主机，或者当识别操作是复制操作时，将读取的数据复制到主机的速度降低。

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