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41. 发明授权

EP3008609B1 CAMERA CONTROL INTERFACE EXTENSION BUS 有权
标题翻译：摄像机控制接口扩展总线
公开(公告)号：EP3008609B1
公开(公告)日：2017-08-30
申请号：EP14737416.9
申请日：2014-06-12
申请人： QUALCOMM Incorporated
发明人： SENGOKU, Shoichiro , WILEY, George Alan , CHEUNG, Joseph
IPC分类号： G06F13/42
CPC分类号： G06F13/4291 , G06F13/364 , G06F13/4282 , G06F13/4295 , H04L7/0331
摘要： System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.
摘要翻译：描述了提供用于集成电路间（I2C）和/或相机控制接口（CCI）操作的串行总线的改进性能的系统，方法和设备。其他描述的设备可以被配置为总线主设备或从设备。在一种方法中，发射机可以从一组比特中生成转换号码，将转换号码转换成符号序列，并且在双线串行总线的信令状态下发送符号序列。定时信息可以在符号序列中的连续码元对符号之间的转换中编码。例如，每个转换可能导致双导线串行总线的至少一条导线的信号状态的改变。接收器可以从转换中导出接收时钟以便接收和解码符号序列。

42. 发明授权

EP2638523B1 PARALLEL IMAGE PROCESSING USING MULTIPLE PROCESSORS 有权
标题翻译：并行图像处理使用多处理器
公开(公告)号：EP2638523B1
公开(公告)日：2017-06-28
申请号：EP11791666.8
申请日：2011-11-07
申请人： Qualcomm Incorporated
发明人： HWANG, Hau , CHEUNG, Joseph , GOMA, Sergiu R.
IPC分类号： G06T1/20
CPC分类号： G06T1/20 , H04N5/2258 , H04N5/23229
摘要： An electronic device for parallel image processing using multiple processors is disclosed. The electronic device includes multiple image sensors for providing image data. The electronic device also includes multiple processors for processing segmented image data to produce processed segmented image data. Each processor is dedicated to one of the image sensors. A multiple processor interface is also included. The multiple processor interface maps the image data to the processors, segments the image data to produce the segmented image data and synchronizes the segmented image data to processor clock rates.
摘要翻译：公开了使用多个处理器的用于并行图像处理的电子设备。电子设备包括用于提供图像数据的多个图像传感器。电子设备还包括用于处理分段图像数据以产生处理后的分段图像数据的多个处理器。每个处理器专用于其中一个图像传感器。多处理器接口也包括在内。多处理器接口将图像数据映射到处理器，分割图像数据以产生分割的图像数据，并将分割的图像数据与处理器时钟速率同步。

43. 发明公开

EP2972928A1 MULTI-WIRE SINGLE-ENDED PUSH-PULL LINK WITH DATA SYMBOL TRANSITION BASED CLOCKING 有权
标题翻译： MEHRADRIGE EINTAKT-PUSH-PULL-VERBINDUNG MIT AUFDATENSYMBOLÜBERGANGBASIERENDER TAKTUNG
公开(公告)号：EP2972928A1
公开(公告)日：2016-01-20
申请号：EP14720762.5
申请日：2014-03-12
申请人： Qualcomm Incorporated
发明人： SENGOKU, Shoichiro , WILEY, George Alan , CHEUNG, Joseph
IPC分类号： G06F13/42 , G06F13/40 , H04L25/00
CPC分类号： H04L7/027 , G06F13/4072 , G06F13/4295 , H04L25/00 , H04L25/14
摘要： System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.
摘要翻译：描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。数据比特序列被转换成M个转换号码，然后转换成符号序列。符号序列通过N线传输。时钟信号可以被有效地嵌入在符号序列的传输中。符号序列中的每一个可以基于M个转换号中的一个和符号序列中的前一个的值来选择。

44. 发明公开

EP2965482A1 TRANSCODING METHOD FOR MULTI-WIRE SIGNALING THAT EMBEDS CLOCK INFORMATION IN TRANSITION OF SIGNAL STATE 审中-公开
标题翻译：反式CODING多核信号方法与嵌入时钟信号，信号状态的过渡
公开(公告)号：EP2965482A1
公开(公告)日：2016-01-13
申请号：EP14715752.3
申请日：2014-03-07
申请人： Qualcomm Incorporated
发明人： SENGOKU, Shoichiro , WILEY, George Alan , LEE, Chulkyu , CHEUNG, Joseph
IPC分类号： H04L25/49 , H04L25/493 , H04L25/02
CPC分类号： H04L7/033 , H03K5/1252 , H03K5/1534 , H04L7/0066 , H04L7/027 , H04L25/0272 , H04L25/14 , H04L25/49 , H04L25/4906 , H04L25/493
摘要： A clock recovery circuit is provided comprising a receiver circuit and a clock extraction circuit. The receiver circuit may be adapted to decode a differentially encoded signal on a plurality of data lines, where at least one data symbol is differentially encoded in state transitions of the differentially encoded signal. The clock extraction circuit may be adapted to obtain a clock signal from state transition signals derived from the state transitions.

45. 发明公开

EP2716052A1 INTERACTIVE USER INTERFACE FOR STEREOSCOPIC EFFECT ADJUSTMENT 审中-公开
标题翻译：交互式用户界面，用于设置立体效果
公开(公告)号：EP2716052A1
公开(公告)日：2014-04-09
申请号：EP12724803.7
申请日：2012-05-17
申请人： Qualcomm Incorporated
发明人： ATANASSOV, Kalin M. , GOMA, Sergiu R. , CHEUNG, Joseph , RAMACHANDRA, Vikas
IPC分类号： H04N13/00 , H04N13/04
CPC分类号： H04N13/398 , H04N13/128
摘要： Present embodiments contemplate systems, apparatus, and methods to determine a user's preference for depicting a stereoscopic effect. Particularly, certain of the embodiments contemplate receiving user input while displaying a stereoscopic video sequence. The user's preferences may be determined based upon the input. These preferences may then be applied to future stereoscopic depictions.

46. 发明公开

EP2638523A1 PARALLEL IMAGE PROCESSING USING MULTIPLE PROCESSORS 有权
标题翻译：平行胆固醇麻醉剂MEHREREN PROZESSOREN
公开(公告)号：EP2638523A1
公开(公告)日：2013-09-18
申请号：EP11791666.8
申请日：2011-11-07
申请人： Qualcomm Incorporated
发明人： HWANG, Hau , CHEUNG, Joseph , GOMA, Sergiu R.
IPC分类号： G06T1/20
CPC分类号： G06T1/20 , H04N5/2258 , H04N5/23229
摘要： An electronic device for parallel image processing using multiple processors is disclosed. The electronic device includes multiple image sensors for providing image data. The electronic device also includes multiple processors for processing segmented image data to produce processed segmented image data. Each processor is dedicated to one of the image sensors. A multiple processor interface is also included. The multiple processor interface maps the image data to the processors, segments the image data to produce the segmented image data and synchronizes the segmented image data to processor clock rates.
摘要翻译：公开了一种使用多个处理器并行图像处理的电子设备。电子设备包括用于提供图像数据的多个图像传感器。电子设备还包括用于处理分段图像数据以产生经处理的分段图像数据的多个处理器。每个处理器专用于其中一个图像传感器。还包括多处理器接口。多处理器接口将图像数据映射到处理器，对图像数据进行分段以产生分割的图像数据，并将分割的图像数据与处理器时钟速率同步。

47. 发明公开

EP2415014A1 APPARATUS AND METHOD TO ROTATE AN IMAGE 审中-公开
标题翻译：装置和方法用于车削的图像
公开(公告)号：EP2415014A1
公开(公告)日：2012-02-08
申请号：EP10712639.3
申请日：2010-03-31
申请人： QUALCOMM Incorporated
发明人： HWANG, Hau , LIU, Shizhong , CHEUNG, Joseph , KIM, Hyung, Cook
IPC分类号： G06T3/60
CPC分类号： G06T3/602
摘要： Image processing systems and methods are disclosed. In a particular embodiment, a method is disclosed that includes receiving image data of an image. The image data includes a plurality of image blocks. The method further includes calculating a first differential DC value during a rotation operation of the image by comparing a first DC coefficient value of a first block of a first row of the image to a second DC coefficient value of a first block of a second row of the image. The method further includes storing the first differential DC value in a memory prior to completing the rotation operation.

48. 发明公开

EP1955551A2 SCALER ARCHITECTURE FOR IMAGE AND VIDEO PROCESSING 审中-公开
标题翻译：扩展体系结构图像和视频处理
公开(公告)号：EP1955551A2
公开(公告)日：2008-08-13
申请号：EP06850850.6
申请日：2006-11-30
申请人： QUALCOMM Incorporated
发明人： CHEUNG, Joseph , KANDHADAI, Ananthapadmanabhan A. , PAN, George Gaozhi , MOHAN, Sumit
IPC分类号： H04N7/26 , H04N7/50
CPC分类号： H04N19/59 , H04N19/156 , H04N19/423 , H04N19/436 , H04N19/61 , H04N19/85
摘要： This disclosure describes a scaler architecture for image and/or video processing. One aspect relates to an apparatus comprising an image processing unit, a memory, and a coder. The memory is configured to store processed image data from the image processing unit. The coder is configured to retrieve the stored, processed image data from the memory. The coder comprises a scaler configured to upscale the retrieved image data from the memory. The coder is configured to encode the scaled image data.

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